Intel Phi 7120A Manuales de usuario

Tabla de contenidos

• 1 Introduction

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  • 1.1 Reference Documentation

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    • Table 1-1. Related Documents

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  • 1.2 Conventions and Terminology

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    • 1.2.1 Terminology

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      • Table 1-2. General Terminology

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• 2 Intel® Xeon Phi™ Coprocessor Architecture

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  • 2.1 Intel® Xeon Phi™ Coprocessor Product Overview

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    • Figure 2-1. Intel® Xeon Phi™ Coprocessor Board Schematic

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    • 2.1.1 Intel® Xeon Phi™ Coprocessor Board Design

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      • Figure 2-2. Intel® Xeon Phi™ Coprocessor Board Top side (for reference only)

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      • Figure 2-3. Intel® Xeon Phi™ Coprocessor Board, Back side (reference only)

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        • Note: Figure 2-2 and 2-3 are representative of the final Intel® Xeon Phi™ Coprocessor board without the package thermal and mechanical solution.

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    • 2.1.2 System Management Controller (SMC)

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    • 2.1.3 Intel® Xeon Phi™ Coprocessor Silicon

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      • Figure 2-4. Intel® Xeon Phi™ Coprocessor Silicon Layout

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    • 2.1.4 Intel® Xeon Phi™ Coprocessor Product Family

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      • Table 2-1. Intel® Xeon Phi™ Coprocessor Product Family

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    • 2.1.5 Intel® Xeon Phi™ Coprocessor 7120D/5120D(Dense Form Factor)

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      • Figure 2-5. 7120D/5120D Dense Form Factor, Topside

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• 3 Thermal and Mechanical Specification

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  • 3.1 Mechanical Specifications

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    • Table 3-1. Intel® Xeon Phi™ Coprocessor Mechanical Specification

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    • Figure 3-1 Location of Mounting Holes on the Intel® Xeon Phi™ Coprocessor Card (in mils)

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    • Figure 3-2 Dimensions of the Intel® Xeon Phi™ Coprocessor Card (in mils)

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  • 3.2 Intel® Xeon Phi™ Coprocessor Thermal Specification

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    • Table 3-2. Intel® Xeon Phi™ Coprocessor Thermal Specification

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    • 3.2.1 Intel® Xeon Phi™ Coprocessor Thermal Management

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      • Figure 3-3 Entering and Exiting Thermal Throttling (PROCHOT)

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  • 3.3 Intel® Xeon Phi™ Coprocessor Thermal Solutions

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    • 3.3.1 3120A and 7120A Active Cooling Solution

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      • Figure 3-4 Exploded View of 3120A / 7120A Active Solution

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    • 3.3.2 7120P/SE10P/5110P/3120P/31S1P Passive Cooling Solution

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      • Figure 3-5 Exploded View of Passive Thermal Solution

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      • 3.3.2.1 System Airflow for 5110P SKUs

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        • Note: For systems with reversed airflow, the corresponding airflow requirement is expected to be within +/-5% tolerance of the values shown in the following tables.

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      • 3.3.2.2 Airflow Requirement for SE10P/7120P/3120P/31S1P Passive Cooling Solution

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        • Figure 3-6 Airflow Requirement vs. 45oC Inlet Temperature for the 5110P at 225W TDP

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        • Figure 3-7 Airflow Requirement vs. Inlet Temperature for the 31S1P at 270W TDP and SE10P/7120P/3120P at 300W TDP

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        • Figure 3-8 Airflow Requirement vs. Inlet Temperature for the 5110P Card at 245W TDP

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  • 3.4 Cooling Solution Guidelines for SE10X/7120X and 7120D/5120D

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    • 3.4.1 Thermal Considerations

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      • Figure 3-9 SE10X/7120X Power Profile for Coprocessor Intensive Workload (all values in Watts)

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      • Figure 3-10 SE10X/7120X Power Profile for Memory Intensive Workload (all values in Watts)

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      • Figure 3-11 5120D Power Profile: Coprocessor Centric (all values in Watts)

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      • Figure 3-12 5120D Power Profile: Memory Centric (all values in Watts)

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      • Figure 3-13 7120D Power Profile: Coprocessor Centric (all values in Watts)

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      • Figure 3-14 7120D Power Profile: Memory Centric (all values in Watts)

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      • Table 3-3. Component Thermal Specification on SE10X/7120X and 7120D/5120D

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      • 3.4.1.1 VR Temperature and Thermal Throttling

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        • Figure 3-15 7120D/5120D VR Thermal Sensors for Custom Cooling Consideration

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    • 3.4.2 Thermal Profile and Cooling

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      • Figure 3-16 SE10X/7120X SKU Coprocessor Junction Temperature (Tjunction) vs Power

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      • Figure 3-17 SE10X/7120X SKU Coprocessor Case Temperature (Tcase) vs Power

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    • 3.4.3 Mechanical Considerations

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      • Table 3-4. Board Component Heights

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      • Figure 3-18 SE10X/7120X Board Top Side

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      • Figure 3-19 SE10X/7120X Board Bottom Side

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      • Figure 3-20 7120D/5120D Board Top Side

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      • Figure 3-21 7120D/5120D Board Bottom Side

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    • 3.4.4 Mechanical Shock and Vibration Testing

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      • Table 3-5. Dynamic Load Shift Specification

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  • 3.5 Intel® Xeon Phi™ Coprocessor PCI Express* Card Extender Bracket Installation

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    • Note: The SE10X/7120X and 7120D/5120D SKUs are not shipped with the extender bracket.

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    • Figure 3-22 Contents of Intel® Xeon Phi™ Coprocessor Package Shipment

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    • 3.5.1 Bracket Installation Steps

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      • 1. Determine Lid Type.

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      • Figure 3-23 Overlap Lid

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      • Figure 3-24 Clearance Lid

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        • 2. Remove Overlap Lid.

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          • a. Remove 2 of the M3x6mm screws retaining the lid, as shown in Figure 3-25.

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      • Figure 3-25 Overlap Lid Removal

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        • b. Remove Lid. Take care not to bend tabs, as shown in Figure 3-26.

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      • Figure 3-26 Tilt Overlap Lid and Slide as shown to Disengage Tabs

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        • 3. Install OEM Bracket.

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          • a. Insert the OEM bracket into the Intel® Xeon Phi™ coprocessor card assembly, as shown in Figure 3-27.

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      • Figure 3-27 OEM Bracket Installation

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        • b. Install (4) M3 x 6mm Flat Head Screws; torque = 6inch-lbs, shown in Figure 3- 28.

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      • Figure 3-28 OEM Bracket Installation

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        • 4. Replace Lid on “Overlap Lid” Units Only

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          • a. Insert tabs into slots in card assembly, shown in Figure 3-29.

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      • Figure 3-29 Replace Lid on “Overlap Lid” Units

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        • b. Install the lid’s screws (M3 x 6mm Flat head); torque = 6 inch-lbs, shown in Figure 3-30.

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      • Figure 3-30 Replace Lid on “Overlap Lid” Units (cont.)

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• 4 Intel® Xeon Phi™ Coprocessor Pin Descriptions

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  • 4.1 PCI Express* Signals

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    • Table 4-1. PCI Express* Connector Signals on the Intel® Xeon Phi™ Coprocessor

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    • 4.1.1 PROCHOT_N (Pin B12)

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  • 4.2 Supplemental Power Connector(s)

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  • 4.3 Dense Form Factor (5120D) Edge Connector Pins

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    • Table 4-2. 5120D (DFF) SKU Pinout

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    • 4.3.1 Baseboard Requirements of 5120D

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      • Table 4-3. 51xxD Power Rail Requirements on Baseboard

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    • 4.3.2 AC Coupling on 5120D Data Pins

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• 5 Power Specification and Management

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  • Table 5-1. Intel® Xeon Phi™ Coprocessor Power States

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  • 5.1 5110P SKU Power Options

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  • 5.2 Intel® Xeon Phi™ Coprocessor Power States

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    • Figure 5-1. Coprocessor in C0-state and Memory in M0-state

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      • Note: No application is expected to dissipate maximum power from cores and memory simultaneously.

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    • Figure 5-2. Some cores are in C0-state and other cores in C1-state; Memory in M0-state

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    • Figure 5-3. All Cores In C1 state; Memory In M1 state

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    • Figure 5-4. All Cores In Package-C3 State; Memory In M1

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    • Figure 5-5. Package-C3 and Memory M2 state

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    • Figure 5-6. Package-C6 and Memory M2 state

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    • Figure 5-7. Package-C6 and Memory M3 state

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  • 5.3 P-states and Turbo Mode

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    • Figure 5-8. Intel® Xeon Phi™ coprocessor P-States and Turbo

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• 6 Manageability

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  • 6.1 Intel® Xeon Phi™ Coprocessor Manageability Architecture

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  • 6.2 System Management Controller (SMC)

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    • Figure 6-1 Intel® Xeon Phi™ Coprocessor System Manageability Architecture

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  • 6.3 General SMC Features and Capabilities

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    • 6.3.1 Catastrophic Shutdown Detection

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  • 6.4 Host / In-Band Management Interface (SCIF)

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  • 6.5 System and Power Management

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  • 6.6 Out of Band / PCI Express* SMBus / IPMB Management Capabilities

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    • 6.6.1 IPMB Protocol

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    • 6.6.2 Polled Master-Only Protocol

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      • 6.6.2.1 Polled Master-Only Protocol Clarifications

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      • 6.6.2.2 SMBus Write and Read Block Command Numbers

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      • 6.6.2.3 Write Description

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        • Table 6-1. SMBus Write Commands

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        • Figure 6-1. Write Block Command Diagram

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      • 6.6.2.4 Read Description

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        • Figure 6-2. Read Block Command Diagram

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    • 6.6.3 Supported IPMI Commands

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      • 6.6.3.1 Miscellaneous Commands

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        • Table 6-2. Miscellaneous Command Details

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      • 6.6.3.2 FRU Related Commands

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        • Table 6-3. FRU Related Command Details

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      • 6.6.3.3 SDR Related Commands

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        • Table 6-4. SDR Related Command Details

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      • 6.6.3.4 SEL Related Commands

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        • Table 6-5. SEL Related Command Details

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      • 6.6.3.5 Sensor Related Commands

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        • Table 6-6. Sensor Related Command Details

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      • 6.6.3.6 General Commands

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        • Table 6-7. General Command Details

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        • 6.6.3.6.1 CPU Package Configuration Read

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        • Table 6-8. CPU Package Config Read Request Format

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        • Table 6-9. CPU Package Config Read Response Format

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        • 6.6.3.6.2 CPU Package Configuration Write

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        • Table 6-10. CPU Package Config Write Request Format

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        • Table 6-11. CPU Package Config Write Response Format

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        • 6.6.3.6.3 Set SM Signal

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        • Table 6-12. Set SM Signal Request Format (Continued)

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        • Table 6-13. Set SM Signal Response Format

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      • 6.6.3.7 OEM Commands

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        • Table 6-14. OEM Command Details

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        • 6.6.3.7.1 OEM Set Fan PWM Adder

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        • Table 6-15. Set Fan PWM Adder Command Request Format

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        • Table 6-16. Set Fan PWM Adder Command Response Format

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        • 6.6.3.7.2 OEM Get POST Register

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        • Table 6-17. Get POST Register Request Format

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        • Table 6-18. Get POST Register Response Format

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        • 6.6.3.7.3 OEM Assert Forced Throttle

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        • Table 6-19. Assert Forced Throttle Request Format

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        • Table 6-20. Assert Forced Throttle Response Format

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        • 6.6.3.7.4 OEM Enable External Throttle

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        • Table 6-21. Enable External Throttle Request Format

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        • Table 6-22. Enable External Throttle Response Format

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        • 6.6.3.7.5 OEM Get Throttle Reason

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        • Table 6-23. OEM Get Throttle Reason Request Format

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        • Table 6-24. OEM Get Throttle Reason Response Format

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      • 6.6.3.8 Other IPMI Related Information

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        • Table 6-25. Table of Sensors

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      • 6.6.3.9 SMC IPMI Discrete Sensors

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        • 6.6.3.9.1 Sensor Status

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        • Table 6-26. Status Sensor Report Format

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  • 6.7 SMC LED_ERROR and Fan PWM

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    • Table 6-27. LED Indicators

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