Manuais de utilizador para Intel Phi 7120A

índice analítico

• 1 Introduction

  7
  • 1.1 Reference Documentation

    7
    • Table 1-1. Related Documents

      7
  • 1.2 Conventions and Terminology

    7
    • 1.2.1 Terminology

      7
      • Table 1-2. General Terminology

        7
• 2 Intel® Xeon Phi™ Coprocessor Architecture

  9
  • 2.1 Intel® Xeon Phi™ Coprocessor Product Overview

    9
    • Figure 2-1. Intel® Xeon Phi™ Coprocessor Board Schematic

      9
    • 2.1.1 Intel® Xeon Phi™ Coprocessor Board Design

      10
      • Figure 2-2. Intel® Xeon Phi™ Coprocessor Board Top side (for reference only)

        11
      • Figure 2-3. Intel® Xeon Phi™ Coprocessor Board, Back side (reference only)

        11
        • Note: Figure 2-2 and 2-3 are representative of the final Intel® Xeon Phi™ Coprocessor board without the package thermal and mechanical solution.

          11
    • 2.1.2 System Management Controller (SMC)

      11
    • 2.1.3 Intel® Xeon Phi™ Coprocessor Silicon

      12
      • Figure 2-4. Intel® Xeon Phi™ Coprocessor Silicon Layout

        12
    • 2.1.4 Intel® Xeon Phi™ Coprocessor Product Family

      13
      • Table 2-1. Intel® Xeon Phi™ Coprocessor Product Family

        13
    • 2.1.5 Intel® Xeon Phi™ Coprocessor 7120D/5120D(Dense Form Factor)

      13
      • Figure 2-5. 7120D/5120D Dense Form Factor, Topside

        14
• 3 Thermal and Mechanical Specification

  15
  • 3.1 Mechanical Specifications

    15
    • Table 3-1. Intel® Xeon Phi™ Coprocessor Mechanical Specification

      15
    • Figure 3-1 Location of Mounting Holes on the Intel® Xeon Phi™ Coprocessor Card (in mils)

      16
    • Figure 3-2 Dimensions of the Intel® Xeon Phi™ Coprocessor Card (in mils)

      17
  • 3.2 Intel® Xeon Phi™ Coprocessor Thermal Specification

    18
    • Table 3-2. Intel® Xeon Phi™ Coprocessor Thermal Specification

      18
    • 3.2.1 Intel® Xeon Phi™ Coprocessor Thermal Management

      18
      • Figure 3-3 Entering and Exiting Thermal Throttling (PROCHOT)

        19
  • 3.3 Intel® Xeon Phi™ Coprocessor Thermal Solutions

    19
    • 3.3.1 3120A and 7120A Active Cooling Solution

      20
      • Figure 3-4 Exploded View of 3120A / 7120A Active Solution

        20
    • 3.3.2 7120P/SE10P/5110P/3120P/31S1P Passive Cooling Solution

      21
      • Figure 3-5 Exploded View of Passive Thermal Solution

        21
      • 3.3.2.1 System Airflow for 5110P SKUs

        21
        • Note: For systems with reversed airflow, the corresponding airflow requirement is expected to be within +/-5% tolerance of the values shown in the following tables.

          21
      • 3.3.2.2 Airflow Requirement for SE10P/7120P/3120P/31S1P Passive Cooling Solution

        22
        • Figure 3-6 Airflow Requirement vs. 45oC Inlet Temperature for the 5110P at 225W TDP

          23
        • Figure 3-7 Airflow Requirement vs. Inlet Temperature for the 31S1P at 270W TDP and SE10P/7120P/3120P at 300W TDP

          24
        • Figure 3-8 Airflow Requirement vs. Inlet Temperature for the 5110P Card at 245W TDP

          25
  • 3.4 Cooling Solution Guidelines for SE10X/7120X and 7120D/5120D

    26
    • 3.4.1 Thermal Considerations

      26
      • Figure 3-9 SE10X/7120X Power Profile for Coprocessor Intensive Workload (all values in Watts)

        26
      • Figure 3-10 SE10X/7120X Power Profile for Memory Intensive Workload (all values in Watts)

        27
      • Figure 3-11 5120D Power Profile: Coprocessor Centric (all values in Watts)

        28
      • Figure 3-12 5120D Power Profile: Memory Centric (all values in Watts)

        29
      • Figure 3-13 7120D Power Profile: Coprocessor Centric (all values in Watts)

        30
      • Figure 3-14 7120D Power Profile: Memory Centric (all values in Watts)

        31
      • Table 3-3. Component Thermal Specification on SE10X/7120X and 7120D/5120D

        32
      • 3.4.1.1 VR Temperature and Thermal Throttling

        32
        • Figure 3-15 7120D/5120D VR Thermal Sensors for Custom Cooling Consideration

          32
    • 3.4.2 Thermal Profile and Cooling

      33
      • Figure 3-16 SE10X/7120X SKU Coprocessor Junction Temperature (Tjunction) vs Power

        33
      • Figure 3-17 SE10X/7120X SKU Coprocessor Case Temperature (Tcase) vs Power

        34
    • 3.4.3 Mechanical Considerations

      35
      • Table 3-4. Board Component Heights

        35
      • Figure 3-18 SE10X/7120X Board Top Side

        36
      • Figure 3-19 SE10X/7120X Board Bottom Side

        37
      • Figure 3-20 7120D/5120D Board Top Side

        38
      • Figure 3-21 7120D/5120D Board Bottom Side

        39
    • 3.4.4 Mechanical Shock and Vibration Testing

      39
      • Table 3-5. Dynamic Load Shift Specification

        39
  • 3.5 Intel® Xeon Phi™ Coprocessor PCI Express* Card Extender Bracket Installation

    40
    • Note: The SE10X/7120X and 7120D/5120D SKUs are not shipped with the extender bracket.

      40
    • Figure 3-22 Contents of Intel® Xeon Phi™ Coprocessor Package Shipment

      40
    • 3.5.1 Bracket Installation Steps

      41
      • 1. Determine Lid Type.

        41
      • Figure 3-23 Overlap Lid

        41
      • Figure 3-24 Clearance Lid

        41
        • 2. Remove Overlap Lid.

          42
          • a. Remove 2 of the M3x6mm screws retaining the lid, as shown in Figure 3-25.

            42
      • Figure 3-25 Overlap Lid Removal

        42
        • b. Remove Lid. Take care not to bend tabs, as shown in Figure 3-26.

          42
      • Figure 3-26 Tilt Overlap Lid and Slide as shown to Disengage Tabs

        42
        • 3. Install OEM Bracket.

          43
          • a. Insert the OEM bracket into the Intel® Xeon Phi™ coprocessor card assembly, as shown in Figure 3-27.

            43
      • Figure 3-27 OEM Bracket Installation

        43
        • b. Install (4) M3 x 6mm Flat Head Screws; torque = 6inch-lbs, shown in Figure 3- 28.

          43
      • Figure 3-28 OEM Bracket Installation

        43
        • 4. Replace Lid on “Overlap Lid” Units Only

          44
          • a. Insert tabs into slots in card assembly, shown in Figure 3-29.

            44
      • Figure 3-29 Replace Lid on “Overlap Lid” Units

        44
        • b. Install the lid’s screws (M3 x 6mm Flat head); torque = 6 inch-lbs, shown in Figure 3-30.

          44
      • Figure 3-30 Replace Lid on “Overlap Lid” Units (cont.)

        44
• 4 Intel® Xeon Phi™ Coprocessor Pin Descriptions

  45
  • 4.1 PCI Express* Signals

    45
    • Table 4-1. PCI Express* Connector Signals on the Intel® Xeon Phi™ Coprocessor

      45
    • 4.1.1 PROCHOT_N (Pin B12)

      46
  • 4.2 Supplemental Power Connector(s)

    47
  • 4.3 Dense Form Factor (5120D) Edge Connector Pins

    47
    • Table 4-2. 5120D (DFF) SKU Pinout

      48
    • 4.3.1 Baseboard Requirements of 5120D

      51
      • Table 4-3. 51xxD Power Rail Requirements on Baseboard

        51
    • 4.3.2 AC Coupling on 5120D Data Pins

      51
• 5 Power Specification and Management

  53
  • Table 5-1. Intel® Xeon Phi™ Coprocessor Power States

    53
  • 5.1 5110P SKU Power Options

    53
  • 5.2 Intel® Xeon Phi™ Coprocessor Power States

    54
    • Figure 5-1. Coprocessor in C0-state and Memory in M0-state

      54
      • Note: No application is expected to dissipate maximum power from cores and memory simultaneously.

        54
    • Figure 5-2. Some cores are in C0-state and other cores in C1-state; Memory in M0-state

      55
    • Figure 5-3. All Cores In C1 state; Memory In M1 state

      55
    • Figure 5-4. All Cores In Package-C3 State; Memory In M1

      56
    • Figure 5-5. Package-C3 and Memory M2 state

      56
    • Figure 5-6. Package-C6 and Memory M2 state

      57
    • Figure 5-7. Package-C6 and Memory M3 state

      57
  • 5.3 P-states and Turbo Mode

    57
    • Figure 5-8. Intel® Xeon Phi™ coprocessor P-States and Turbo

      59
• 6 Manageability

  61
  • 6.1 Intel® Xeon Phi™ Coprocessor Manageability Architecture

    61
  • 6.2 System Management Controller (SMC)

    61
    • Figure 6-1 Intel® Xeon Phi™ Coprocessor System Manageability Architecture

      62
  • 6.3 General SMC Features and Capabilities

    63
    • 6.3.1 Catastrophic Shutdown Detection

      63
  • 6.4 Host / In-Band Management Interface (SCIF)

    64
  • 6.5 System and Power Management

    65
  • 6.6 Out of Band / PCI Express* SMBus / IPMB Management Capabilities

    66
    • 6.6.1 IPMB Protocol

      67
    • 6.6.2 Polled Master-Only Protocol

      67
      • 6.6.2.1 Polled Master-Only Protocol Clarifications

        67
      • 6.6.2.2 SMBus Write and Read Block Command Numbers

        68
      • 6.6.2.3 Write Description

        68
        • Table 6-1. SMBus Write Commands

          68
        • Figure 6-1. Write Block Command Diagram

          68
      • 6.6.2.4 Read Description

        69
        • Figure 6-2. Read Block Command Diagram

          69
    • 6.6.3 Supported IPMI Commands

      69
      • 6.6.3.1 Miscellaneous Commands

        69
        • Table 6-2. Miscellaneous Command Details

          69
      • 6.6.3.2 FRU Related Commands

        69
        • Table 6-3. FRU Related Command Details

          69
      • 6.6.3.3 SDR Related Commands

        70
        • Table 6-4. SDR Related Command Details

          70
      • 6.6.3.4 SEL Related Commands

        70
        • Table 6-5. SEL Related Command Details

          70
      • 6.6.3.5 Sensor Related Commands

        70
        • Table 6-6. Sensor Related Command Details

          70
      • 6.6.3.6 General Commands

        71
        • Table 6-7. General Command Details

          71
        • 6.6.3.6.1 CPU Package Configuration Read

          71
        • Table 6-8. CPU Package Config Read Request Format

          71
        • Table 6-9. CPU Package Config Read Response Format

          71
        • 6.6.3.6.2 CPU Package Configuration Write

          72
        • Table 6-10. CPU Package Config Write Request Format

          72
        • Table 6-11. CPU Package Config Write Response Format

          72
        • 6.6.3.6.3 Set SM Signal

          72
        • Table 6-12. Set SM Signal Request Format (Continued)

          72
        • Table 6-13. Set SM Signal Response Format

          73
      • 6.6.3.7 OEM Commands

        73
        • Table 6-14. OEM Command Details

          73
        • 6.6.3.7.1 OEM Set Fan PWM Adder

          73
        • Table 6-15. Set Fan PWM Adder Command Request Format

          73
        • Table 6-16. Set Fan PWM Adder Command Response Format

          74
        • 6.6.3.7.2 OEM Get POST Register

          74
        • Table 6-17. Get POST Register Request Format

          74
        • Table 6-18. Get POST Register Response Format

          74
        • 6.6.3.7.3 OEM Assert Forced Throttle

          74
        • Table 6-19. Assert Forced Throttle Request Format

          74
        • Table 6-20. Assert Forced Throttle Response Format

          74
        • 6.6.3.7.4 OEM Enable External Throttle

          74
        • Table 6-21. Enable External Throttle Request Format

          75
        • Table 6-22. Enable External Throttle Response Format

          75
        • 6.6.3.7.5 OEM Get Throttle Reason

          75
        • Table 6-23. OEM Get Throttle Reason Request Format

          75
        • Table 6-24. OEM Get Throttle Reason Response Format

          75
      • 6.6.3.8 Other IPMI Related Information

        75
        • Table 6-25. Table of Sensors

          76
      • 6.6.3.9 SMC IPMI Discrete Sensors

        77
        • 6.6.3.9.1 Sensor Status

          77
        • Table 6-26. Status Sensor Report Format

          77
  • 6.7 SMC LED_ERROR and Fan PWM

    78
    • Table 6-27. LED Indicators

      78