Microchip Technology MA330019-2 Manuales de usuario

Tabla de contenidos

• 16-bit Digital Signal Controllers (up to 128 KB Flash and 16K SRAM) with Advanced Analog

  1
• 1.0 Device Overview

  13
  • FIGURE 1-1: dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, and dsPIC33FJ128GPX02/ X04 Block Diagram

    14
  • TABLE 1-1: Pinout I/O Descriptions (Continued)

    15
• 2.0 Guidelines for Getting Started with 16-bit Digital Signal Controllers

  19
  • 2.1 Basic Connection Requirements

    19
  • 2.2 Decoupling Capacitors

    19
    • FIGURE 2-1: Recommended Minimum Connection

      20
  • 2.3 CPU Logic Filter Capacitor Connection (Vcap)

    20
  • 2.4 Master Clear (MCLR) Pin

    20
    • FIGURE 2-2: Example of MCLR Pin Connections

      20
  • 2.5 ICSP Pins

    21
  • 2.6 External Oscillator Pins

    21
    • FIGURE 2-3: Suggested Placement of the Oscillator Circuit

      21
    • TABLE 2-1: Crystal Recommendations

      21
    • TABLE 2-2: Resonator Recommendations

      22
  • 2.7 Oscillator Value Conditions on Device Start-up

    22
  • 2.8 Configuration of Analog and Digital Pins During ICSP Operations

    22
  • 2.9 Unused I/Os

    22
• 3.0 CPU

  23
  • 3.1 Overview

    23
  • 3.2 Data Addressing Overview

    23
  • 3.3 DSP Engine Overview

    23
  • 3.4 Special MCU Features

    24
    • FIGURE 3-1: dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, and dsPIC33FJ128GPX02/ X04 CPU Core Block Diagram

      24
    • FIGURE 3-2: dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, and dsPIC33FJ128GPX02/ X04 Programmer’s Model

      25
  • 3.5 CPU Resources

    26
  • 3.6 CPU Control Registers

    27
    • Register 3-1: SR: CPU Status Register (Continued)

      27
    • Register 3-2: CORCON: Core Control Register

      29
  • 3.7 Arithmetic Logic Unit (ALU)

    30
  • 3.8 DSP Engine

    30
    • TABLE 3-1: DSP Instructions Summary

      30
    • FIGURE 3-3: DSP Engine Block Diagram

      31
• 4.0 Memory Organization

  35
  • 4.1 Program Address Space

    35
    • FIGURE 4-1: Program Memory Map for dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/ X04, and dsPIC33FJ128GPX02/X04 Devices

      35
    • FIGURE 4-2: Program Memory Organization

      36
  • 4.2 Data Address Space

    37
    • FIGURE 4-3: Data Memory Map for dsPIC33FJ32GP302/304 Devices with 4 Kb RAM

      38
    • FIGURE 4-4: Data Memory Map for dsPIC33FJ128GP202/204 and dsPIC33FJ64GP202/ 204 Devices with 8 Kb RAM

      39
    • FIGURE 4-5: Data Memory Map for dsPIC33FJ128GP802/804 And dsPIC33FJ64GP802/ 804 Devices with 16 Kb RAM

      40
  • 4.3 Memory Resources

    41
  • 4.4 Special Function Register Maps

    42
    • TABLE 4-1: CPU Core Registers Map (Continued)

      42
    • TABLE 4-2: Change Notification Register Map for dsPIC33FJ128GP202/802, dsPIC33FJ64GP202/802 and dsPIC33FJ32GP302

      44
    • TABLE 4-3: Change Notification Register Map for dsPIC33FJ128GP204/804, dsPIC33FJ64GP204/804 and dsPIC33FJ32GP304

      44
    • TABLE 4-4: Interrupt Controller Register Map

      45
    • TABLE 4-5: Timer Register Map

      46
    • TABLE 4-6: Input Capture Register Map

      46
    • TABLE 4-7: Output Compare Register Map

      47
    • TABLE 4-8: I2C1 Register Map

      47
    • TABLE 4-9: UART1 Register Map

      47
    • TABLE 4-10: UART2 Register Map

      48
    • TABLE 4-11: SPI1 Register Map

      48
    • TABLE 4-12: SPI2 Register Map

      48
    • TABLE 4-13: ADC1 Register Map for dsPIC33FJ64GP202/802, dsPIC33FJ128GP202/802 and dsPIC33FJ32GP302

      49
    • TABLE 4-14: ADC1 Register Map for dsPIC33FJ64GP204/804, dsPIC33FJ128GP204/804 and dsPIC33FJ32GP304

      49
    • TABLE 4-15: DAC1 Register Map for dsPIC33FJ128GP802/804 and dsPIC33FJ64GP802/804

      49
    • TABLE 4-16: DMA Register Map (Continued)

      50
    • TABLE 4-17: ECAN1 Register Map When C1CTRL1.WIN = 0 or 1 (For dsPIC33FJ128GP802/804 and dsPIC33FJ64GP802/804)

      52
    • TABLE 4-18: ECAN1 Register Map When C1CTRL1.WIN = 0 (For dsPIC33FJ128GP802/804 and dsPIC33FJ64GP802/804)

      52
    • TABLE 4-19: ECAN1 Register Map When C1CTRL1.WIN = 1(For dsPIC33FJ128GP802/804 and dsPIC33FJ64GP802/804) (Continued)

      53
    • TABLE 4-20: DCI Register Map

      54
    • TABLE 4-21: PERIPHERAL pin Select Input Register Map

      55
    • TABLE 4-22: PERIPHERAL Pin Select Output Register Map for dsPIC33FJ128GP202/802, dsPIC33FJ64GP202/802 and dsPIC33FJ32GP302

      56
    • TABLE 4-23: Peripheral Pin Select Output Register Map for dsPIC33FJ128GP204/804, dsPIC33FJ64GP204/804 and dsPIC33FJ32GP304

      56
    • TABLE 4-24: Parallel Master/Slave Port Register Map for dsPIC33FJ128GP202/802, dsPIC33FJ64GP202/802 and dsPIC33FJ32GP302

      57
    • TABLE 4-25: Parallel Master/Slave Port Register Map for dsPIC33FJ128GP204/804, dsPIC33FJ64GP204/804 and dsPIC33FJ32GP304

      57
    • TABLE 4-26: Real-Time Clock and Calendar Register Map

      58
    • TABLE 4-27: CRC Register Map

      58
    • TABLE 4-28: Dual Comparator Register Map

      58
    • TABLE 4-29: PORTA Register Map for dsPIC33FJ128GP202/802, dsPIC33FJ64GP202/802 and dsPIC33FJ32Gp302

      58
    • TABLE 4-30: PORTA Register Map for dsPIC33FJ128GP204/804, dsPIC33FJ64GP204/804 and dsPIC33FJ32GP304

      59
    • TABLE 4-31: PORTB Register Map

      59
    • TABLE 4-32: PORTC Register Map for dsPIC33FJ128GP204/804, dsPIC33FJ64GP204/804 and dsPIC33FJ32GP304

      59
    • TABLE 4-33: System Control Register Map

      60
    • TABLE 4-34: Security Register Map(1)

      60
    • TABLE 4-35: NVM Register Map

      60
    • TABLE 4-36: PMD Register Map

      60
    • FIGURE 4-6: CALL Stack Frame

      61
  • 4.5 Instruction Addressing Modes

    61
    • TABLE 4-37: Fundamental Addressing Modes Supported

      62
  • 4.6 Modulo Addressing

    63
    • FIGURE 4-7: Modulo Addressing Operation Example

      63
  • 4.7 Bit-Reversed Addressing

    64
    • FIGURE 4-8: Bit-Reversed Address Example

      65
    • TABLE 4-38: Bit-Reversed Address Sequence (16-Entry)

      65
  • 4.8 Interfacing Program and Data Memory Spaces

    66
    • TABLE 4-39: Program Space Address Construction

      66
    • FIGURE 4-9: Data Access from Program Space Address Generation

      67
    • FIGURE 4-10: Accessing Program Memory with Table Instructions

      68
    • FIGURE 4-11: Program Space Visibility Operation

      69
• 5.0 Flash Program Memory

  71
  • 5.1 Table Instructions and Flash Programming

    71
    • FIGURE 5-1: Addressing for Table Registers

      71
  • 5.2 RTSP Operation

    72
  • 5.3 Programming Operations

    72
    • EQUATION 5-1: Programming Time

      72
    • EQUATION 5-2: Minimum Row Write Time

      72
    • EQUATION 5-3: Maximum Row Write Time

      72
  • 5.4 Control Registers

    72
  • 5.5 Flash Resources

    72
  • 5.6 Flash Control Registers

    73
    • Register 5-1: NVMCON: Flash Memory Control Register

      73
    • Register 5-2: NVMKEY: NonVolatile Memory Key RegisteR

      74
    • EXAMPLE 5-1: Erasing a Program Memory Page

      75
    • EXAMPLE 5-2: Loading the Write Buffers

      76
    • EXAMPLE 5-3: Initiating a Programming Sequence

      76
• 6.0 Resets

  77
  • FIGURE 6-1: Reset System Block Diagram

    77
  • 6.1 Reset Resources

    78
  • 6.2 Reset Control Registers

    79
    • Register 6-1: RCON: Reset Control Register(1) (Continued)

      79
  • 6.3 System Reset

    81
    • TABLE 6-1: Oscillator Delay

      81
    • FIGURE 6-2: System Reset Timing

      82
    • TABLE 6-2: Oscillator Delay

      83
  • 6.4 Power-on Reset (POR)

    83
  • 6.4.1 Brown-out Reset (BOR) and Power-up timer (PWRT)

    83
    • FIGURE 6-3: Brown-out Situations

      84
  • 6.5 External Reset (EXTR)

    84
  • 6.6 Software RESET Instruction (SWR)

    84
  • 6.7 Watchdog Time-out Reset (WDTO)

    84
  • 6.8 Trap Conflict Reset

    84
  • 6.9 Configuration Mismatch Reset

    85
  • 6.10 Illegal Condition Device Reset

    85
  • 6.11 Using the RCON Status Bits

    85
    • TABLE 6-3: Reset Flag Bit Operation

      85
• 7.0 Interrupt Controller

  87
  • 7.1 Interrupt Vector Table

    87
  • 7.2 Reset Sequence

    87
    • FIGURE 7-1: dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, and dsPIC33FJ128GPX02/ X04 Interrupt Vector Table

      88
    • TABLE 7-1: Interrupt Vectors (Continued)

      89
  • 7.3 Interrupt Control and Status Registers

    91
  • 7.4 Interrupts Resources

    91
  • 7.5 CPU Registers

    92
    • Register 7-1: SR: CPU STATUS Register(1)

      92
    • Register 7-2: CORCON: CORE Control Register(1)

      92
    • Register 7-3: INTCON1: Interrupt Control Register 1 (Continued)

      93
    • Register 7-4: INTCON2: Interrupt Control Register 2

      95
    • Register 7-5: IFS0: Interrupt Flag Status Register 0 (Continued)

      96
    • Register 7-6: IFS1: Interrupt Flag Status Register 1 (Continued)

      98
    • Register 7-7: IFS2: Interrupt Flag Status Register 2

      100
    • Register 7-8: IFS3: Interrupt Flag Status Register 3

      101
    • Register 7-9: IFS4: Interrupt Flag Status Register 4

      102
    • Register 7-10: IEC0: Interrupt Enable Control Register 0 (Continued)

      103
    • Register 7-11: IEC1: Interrupt Enable Control Register 1 (Continued)

      105
    • Register 7-12: IEC2: Interrupt Enable Control Register 2

      107
    • Register 7-13: IEC3: Interrupt Enable Control Register 3

      108
    • Register 7-14: IEC4: Interrupt Enable Control Register 4

      109
    • Register 7-15: IPC0: Interrupt Priority Control Register 0

      110
    • Register 7-16: IPC1: Interrupt Priority Control Register 1

      111
    • Register 7-17: IPC2: Interrupt Priority Control Register 2

      112
    • Register 7-18: IPC3: Interrupt Priority Control Register 3

      113
    • Register 7-19: IPC4: Interrupt Priority Control Register 4

      114
    • Register 7-20: IPC5: Interrupt Priority Control Register 5

      115
    • Register 7-21: IPC6: Interrupt Priority Control Register 6

      116
    • Register 7-22: IPC7: Interrupt Priority Control Register 7

      117
    • Register 7-23: IPC8: Interrupt Priority Control Register 8

      118
    • Register 7-24: IPC9: Interrupt Priority Control Register 9

      119
    • Register 7-25: IPC11: Interrupt Priority Control Register 11

      120
    • Register 7-26: IPC14: Interrupt Priority Control Register 14

      121
    • Register 7-27: IPC15: Interrupt Priority Control Register 15

      122
    • Register 7-28: IPC16: Interrupt Priority Control Register 16

      123
    • Register 7-29: IPC17: Interrupt Priority Control Register 17

      124
    • Register 7-30: IPC19: Interrupt Priority Control Register 19

      125
    • Register 7-31: INTTREG: Interrupt Control and Status Register

      126
  • 7.6 Interrupt Setup Procedures

    127
• 8.0 Direct Memory Access (DMA)

  129
  • TABLE 8-1: DMA Channel to Peripheral Associations

    129
  • FIGURE 8-1: Top Level System Architecture Using a Dedicated Transaction Bus

    130
  • 8.1 DMA Resources

    131
  • 8.2 DMAC Registers

    131
  • 8.3 DMA Control Registers

    132
    • Register 8-1: DMAxCON: DMA Channel x Control Register

      132
    • Register 8-2: DMAxREQ: DMA Channel x IRQ Select Register

      133
    • Register 8-3: DMAxSTA: DMA Channel x RAM Start Address Register A(1)

      134
    • Register 8-4: DMAxSTB: DMA Channel x RAM Start Address Register B(1)

      134
    • Register 8-5: DMAxPAD: DMA Channel x Peripheral Address Register(1)

      135
    • Register 8-6: DMAxCNT: DMA Channel x Transfer Count Register(1)

      135
    • Register 8-7: DMACS0: DMA Controller Status Register 0 (Continued)

      136
    • Register 8-8: DMACS1: DMA Controller Status Register 1

      138
    • Register 8-9: DSADR: Most Recent DMA RAM Address

      139
• 9.0 Oscillator Configuration

  141
  • FIGURE 9-1: dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, and dsPIC33FJ128GPX02/ X04 Oscillator System Diagram

    141
  • 9.1 CPU Clocking System

    142
    • EQUATION 9-1: Device Operating Frequency

      142
    • EQUATION 9-2: Fosc Calculation

      143
    • EQUATION 9-3: XT with PLL Mode Example

      143
    • FIGURE 9-2: dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, and dsPIC33FJ128GPX02/ X04 PLL Block Diagram

      143
    • TABLE 9-1: Configuration Bit Values for Clock Selection

      144
  • 9.2 Oscillator Resources

    144
  • 9.3 Oscillator Control Registers

    145
    • Register 9-1: OSCCON: Oscillator Control Register(1,3) (Continued)

      145
    • Register 9-2: CLKDIV: Clock Divisor Register(2)

      147
    • Register 9-3: PLLFBD: PLL Feedback Divisor Register(1)

      148
    • Register 9-4: OSCTUN: FRC Oscillator Tuning Register(2)

      149
    • Register 9-5: ACLKCON: Auxiliary Control Register(1)

      150
  • 9.4 Clock Switching Operation

    151
  • 9.5 Fail-Safe Clock Monitor (FSCM)

    151
• 10.0 Power-Saving Features

  153
  • 10.1 Clock Frequency and Clock Switching

    153
  • 10.2 Instruction-Based Power-Saving Modes

    153
    • EXAMPLE 10-1: PWRSAV Instruction Syntax

      153
  • 10.3 Doze Mode

    154
  • 10.4 Peripheral Module Disable

    154
  • 10.5 Power-Saving Resources

    155
  • 10.6 Power-Saving Control Registers

    156
    • Register 10-1: PMD1: Peripheral Module Disable Control Register 1

      156
    • Register 10-2: PMD2: Peripheral Module Disable Control Register 2

      157
    • Register 10-3: PMD3: Peripheral Module Disable Control Register 3

      158
• 11.0 I/O Ports

  159
  • 11.1 Parallel I/O (PIO) Ports

    159
    • FIGURE 11-1: Block Diagram of a Typical Shared Port Structure

      159
  • 11.2 Open-Drain Configuration

    160
  • 11.3 Configuring Analog Port Pins

    160
  • 11.4 I/O Port Write/Read Timing

    160
  • 11.5 Input Change Notification

    160
    • EXAMPLE 11-1: Port Write/Read Example

      160
  • 11.6 Peripheral Pin Select

    161
    • FIGURE 11-2: Remappable MUX Input for U1RX

      161
    • TABLE 11-1: Selectable Input Sources (Maps Input to Function)(1)

      162
    • FIGURE 11-3: Multiplexing of Remappable Output for RPn

      163
    • TABLE 11-2: Output Selection for Remappable Pin (RPn)

      163
  • 11.7 I/O Helpful Tips

    165
  • 11.8 I/O Resources

    165
  • 11.9 Peripheral Pin Select Registers

    166
    • Register 11-1: RPINR0: Peripheral Pin Select Input Register 0

      166
    • Register 11-2: RPINR1: Peripheral Pin Select Input Register 1

      167
    • Register 11-3: RPINR3: Peripheral Pin Select Input Register 3

      168
    • Register 11-4: RPINR4: Peripheral Pin Select Input Register 4

      169
    • Register 11-5: RPINR7: Peripheral Pin Select Input Register 7

      170
    • Register 11-6: RPINR10: Peripheral Pin Select Input Register 10

      171
    • Register 11-7: RPINR11: Peripheral Pin Select Input Register 11

      172
    • Register 11-8: RPINR18: Peripheral Pin Select Input Register 18

      173
    • Register 11-9: RPINR19: Peripheral Pin Select Input Register 19

      174
    • Register 11-10: RPINR20: Peripheral Pin Select Input Register 20

      175
    • Register 11-11: RPINR21: Peripheral Pin Select Input Register 21

      176
    • Register 11-12: RPINR22: Peripheral Pin Select Input Register 22

      177
    • Register 11-13: RPINR23: Peripheral Pin Select Input Register 23

      178
    • Register 11-14: RPINR24: Peripheral Pin Select Input Register 24

      179
    • Register 11-15: RPINR25: Peripheral Pin Select Input Register 25

      180
    • Register 11-16: RPINR26: Peripheral Pin Select Input Register 26(1)

      180
    • Register 11-17: RPOR0: Peripheral Pin Select Output Register 0

      181
    • Register 11-18: RPOR1: Peripheral Pin Select Output Register 1

      181
    • Register 11-19: RPOR2: Peripheral Pin Select Output Register 2

      182
    • Register 11-20: RPOR3: Peripheral Pin Select Output Register 3

      182
    • Register 11-21: RPOR4: Peripheral Pin Select Output Register 4

      183
    • Register 11-22: RPOR5: Peripheral Pin Select Output Register 5

      183
    • Register 11-23: RPOR6: Peripheral Pin Select Output Register 6

      184
    • Register 11-24: RPOR7: Peripheral Pin Select Output Register 7

      184
    • Register 11-25: RPOR8: Peripheral Pin Select Output Register 8(1)

      185
    • Register 11-26: RPOR9: Peripheral Pin Select Output Register 9(1)

      185
    • Register 11-27: RPOR10: Peripheral Pin Select Output Register 10(1)

      186
    • Register 11-28: RPOR11: Peripheral Pin Select Output Register 11(1)

      186
    • Register 11-29: RPOR12: Peripheral Pin Select Output Register 12(1)

      187
• 12.0 Timer1

  189
  • TABLE 12-1: Timer Mode Settings

    189
  • FIGURE 12-1: 16-bit Timer1 Module Block Diagram

    189
  • 12.1 Timer Resources

    190
  • 12.2 Timer1 Control Register

    191
    • Register 12-1: T1CON: Timer1 Control Register

      191
• 13.0 Timer2/3 and Timer4/5 Feature

  193
  • FIGURE 13-1: Type B Timer Block Diagram (x = 2 or 4)

    193
  • FIGURE 13-2: Type C Timer Block Diagram (X = 3 or 5)

    193
  • TABLE 13-1: Timer Mode Settings

    194
  • 13.1 16-bit Operation

    194
  • 13.2 32-bit Operation

    194
    • TABLE 13-2: 32-bit Timer

      194
    • FIGURE 13-3: 32-bit Timer Block Diagram

      195
  • 13.3 Timer Resources

    195
  • 13.4 Timerx/y Control Registers

    196
    • Register 13-1: TxCON: Timer Control Register (x = 2 or 4, y = 3 or 5)

      196
    • Register 13-2: TXCON: Timer Control Register (X = 3 or 5)

      197
• 14.0 Input Capture

  199
  • FIGURE 14-1: Input Capture Block Diagram

    199
  • 14.1 Input Capture Resources

    200
  • 14.2 Input Capture Registers

    201
    • Register 14-1: ICxCON: Input Capture x Control Register (x = 1, 2, 7 or 8)

      201
• 15.0 Output Compare

  203
  • FIGURE 15-1: Output Compare Module Block Diagram

    203
  • 15.1 Output Compare Modes

    204
    • TABLE 15-1: Output Compare Modes

      204
    • FIGURE 15-2: Output Compare Operation

      204
  • 15.2 Output Compare Resources

    205
  • 15.3 Output Compare Control Register

    206
    • Register 15-1: OCxCON: Output Compare x Control Register (x = 1, 2, 3 or 4)

      206
• 16.0 Serial Peripheral Interface (SPI)

  207
  • FIGURE 16-1: SPI Module Block Diagram

    207
  • 16.1 SPI Helpful Tips

    208
  • 16.2 SPI Resources

    208
  • 16.3 SPI Control Registers

    209
    • Register 16-1: SPIxSTAT: SPIx Status and Control Register

      209
    • Register 16-2: SPIxCON1: SPIx Control Register 1 (Continued)

      210
    • Register 16-3: SPIxCON2: SPIx Control Register 2

      212
• 17.0 Inter-Integrated Circuit™ (I2C™)

  213
  • 17.1 Operating Modes

    213
    • FIGURE 17-1: I2C™ Block Diagram (x = 1)

      214
  • 17.2 I2C Resources

    215
  • 17.3 I2C Registers

    215
    • Register 17-1: I2CxCON: I2Cx Control Register (Continued)

      216
    • Register 17-2: I2CxSTAT: I2Cx Status Register (Continued)

      218
    • Register 17-3: I2CxMSK: I2Cx Slave Mode Address Mask Register

      220
• 18.0 Universal Asynchronous Receiver Transmitter (UART)

  221
  • FIGURE 18-1: UART Simplified Block Diagram

    221
  • 18.1 UART Helpful Tips

    222
  • 18.2 UART Resources

    222
  • 18.3 UART Control Registers

    223
    • Register 18-1: UxMODE: UARTx Mode Register (Continued)

      223
    • Register 18-2: UxSTA: UARTx Status and Control Register (Continued)

      225
• 19.0 Enhanced CAN (ECAN™) Module

  227
  • 19.1 Overview

    227
  • 19.2 Frame Types

    228
    • FIGURE 19-1: ECAN™ Module Block Diagram

      229
  • 19.3 Modes of Operation

    230
  • 19.4 ECAN Resources

    231
  • 19.5 ECAN Control Registers

    232
    • Register 19-1: CiCTRL1: ECAN™ Control Register 1

      232
    • Register 19-2: CiCTRL2: ECAN™ Control Register 2

      233
    • Register 19-3: CiVEC: ECAN™ Interrupt Code Register

      234
    • Register 19-4: CiFCTRL: ECAN™ FIFO Control Register

      235
    • Register 19-5: CiFIFO: ECAN™ FIFO Status Register

      236
    • Register 19-6: CiINTF: ECAN™ Interrupt Flag Register

      237
    • Register 19-7: CiINTE: ECAN™ Interrupt Enable Register

      238
    • Register 19-8: CiEC: ECAN™ Transmit/Receive Error Count Register

      239
    • Register 19-9: CiCFG1: ECAN™ Baud Rate Configuration Register 1

      239
    • Register 19-10: CiCFG2: ECAN™ Baud Rate Configuration Register 2

      240
    • Register 19-11: CiFEN1: ECAN™ Acceptance Filter Enable Register

      241
    • Register 19-12: CiBUFPNT1: ECAN™ Filter 0-3 Buffer Pointer Register

      241
    • Register 19-13: CiBUFPNT2: ECAN™ Filter 4-7 Buffer Pointer Register

      242
    • Register 19-14: CiBUFPNT3: ECAN™ Filter 8-11 Buffer Pointer Register

      242
    • Register 19-15: CiBUFPNT4: ECAN™ Filter 12-15 Buffer Pointer Register

      243
    • Register 19-16: CiRXFnSID: ECAN™ Acceptance Filter Standard Identifier Register n (n = 0-15)

      244
    • Register 19-17: CiRXFnEID: ECAN™ Acceptance Filter Extended Identifier Register n (n = 0-15)

      245
    • Register 19-18: CiFMSKSEL1: ECAN™ Filter 7-0 Mask Selection Register

      245
    • Register 19-19: CiFMSKSEL2: ECAN™ Filter 15-8 Mask Selection Register

      246
    • Register 19-20: CiRXMnSID: ECAN™ Acceptance Filter Mask Standard Identifier Register n (n = 0-2)

      247
    • Register 19-21: CiRXMnEID: ECAN™ Acceptance Filter Mask Extended Identifier Register n (n = 0-2)

      247
    • Register 19-22: CiRXFUL1: ECAN™ Receive Buffer Full Register 1

      248
    • Register 19-23: CiRXFUL2: ECAN™ Receive Buffer Full Register 2

      248
    • Register 19-24: CiRXOVF1: ECAN™ Receive Buffer Overflow Register 1

      249
    • Register 19-25: CiRXOVF2: ECAN™ Receive Buffer Overflow Register 2

      249
    • Register 19-26: CiTRmnCON: ECAN™ TX/RX Buffer m Control Register (m = 0,2,4,6; n = 1,3,5,7)

      250
  • 19.6 ECAN Message Buffers

    251
• 20.0 Data Converter Interface (DCI) Module

  255
  • 20.1 Module Introduction

    255
    • FIGURE 20-1: DCI Module Block Diagram

      255
  • 20.2 DCI Resources

    256
  • 20.3 DCI Control Registers

    257
    • Register 20-1: DCICON1: DCI Control Register 1

      257
    • Register 20-2: DCICON2: DCI Control Register 2

      258
    • Register 20-3: DCICON3: DCI Control Register 3

      259
    • Register 20-4: DCISTAT: DCI Status Register

      260
    • Register 20-5: RSCON: DCI Receive Slot Control Register

      261
    • Register 20-6: TSCON: DCI Transmit Slot Control Register

      261
• 21.0 10-bit/12-bit Analog-to- Digital Converter (ADC)

  263
  • 21.1 Key Features

    263
  • 21.2 ADC Initialization

    263
  • 21.3 ADC and DMA

    263
    • FIGURE 21-1: ADC1 Module Block Diagram for dsPIC33FJ32GP304, dsPIC33FJ64GP204/804 and dsPIC33FJ128GP204/804 Devices

      264
    • FIGURE 21-2: ADC1 Module Block Diagram for dsPIC33FJ32GP302, dsPIC33FJ64GP202/802 and dsPIC33FJ128GP202/802 Devices

      265
    • FIGURE 21-3: ADC Conversion Clock Period Block Diagram

      266
  • 21.4 ADC Helpful Tips

    267
  • 21.5 ADC Resources

    267
  • 21.6 ADC Control Registers

    268
    • Register 21-1: AD1CON1: ADC1 Control Register 1 (Continued)

      268
    • Register 21-2: AD1CON2: ADC1 Control Register 2

      270
    • Register 21-3: AD1CON3: ADC1 Control Register 3

      271
    • Register 21-4: AD1CON4: ADC1 Control Register 4

      272
    • Register 21-5: AD1CHS123: ADC1 Input Channel 1, 2, 3 Select Register

      273
    • Register 21-6: AD1CHS0: ADC1 Input Channel 0 Select Register

      274
    • Register 21-7: AD1CSSL: ADC1 Input Scan Select Register Low(1,2)

      275
    • Register 21-8: AD1PCFGL: ADC1 Port Configuration Register Low(1,2,3)

      275
• 22.0 Audio Digital-to-Analog Converter (DAC)

  277
  • 22.1 Key Features

    277
  • 22.2 DAC Module Operation

    277
  • 22.3 DAC Output Format

    277
  • 22.4 DAC Clock

    278
    • FIGURE 22-1: Block Diagram of Audio Digital-to-Analog (DAC) Converter

      278
    • FIGURE 22-2: Audio DAC Output for Ramp Input (Unsigned)

      278
  • 22.5 DAC Resources

    279
  • 22.6 DAC Control Registers

    280
    • Register 22-1: DAC1CON: DAC Control Register

      280
    • Register 22-2: DAC1STAT: DAC Status Register

      281
    • Register 22-3: DAC1DFLT: DAC Default Data Register

      282
    • Register 22-4: DAC1LDAT: DAC Left Data Register

      282
    • Register 22-5: DAC1RDAT: DAC Right Data Register

      282
• 23.0 Comparator Module

  283
  • FIGURE 23-1: Comparator I/O Operating Modes

    283
  • 23.1 Comparator Resources

    284
  • 23.2 Comparator Control Register

    285
    • Register 23-1: CMCON: Comparator Control Register (Continued)

      285
  • 23.3 Comparator Voltage Reference

    287
    • FIGURE 23-2: Comparator Voltage Reference Block Diagram

      287
    • Register 23-2: CVRCON: Comparator Voltage Reference Control Register

      288
• 24.0 Real-Time Clock and Calendar (RTCC)

  289
  • FIGURE 24-1: RTCC Block Diagram

    289
  • 24.1 RTCC Module Registers

    290
    • TABLE 24-1: RTCVAL Register Mapping

      290
    • TABLE 24-2: ALRMVAL Register Mapping

      290
    • EXAMPLE 24-1: Setting the RTCWREN Bit

      290
  • 24.2 RTCC Resources

    291
  • 24.3 RTCC Registers

    292
    • Register 24-1: RCFGCAL: RTCC Calibration and Configuration RegistER(1) (Continued)

      292
    • Register 24-2: PADCFG1: Pad Configuration Control Register

      294
    • Register 24-3: ALCFGRPT: Alarm Configuration Register

      295
    • Register 24-4: RTCVAL (When RTCPTR<1:0> = 11): Year Value Register(1)

      296
    • Register 24-5: RTCVAL (When RTCPTR<1:0> = 10): Month and Day Value Register(1)

      296
    • Register 24-6: RTCVAL (When RTCPTR<1:0> = 01): WKDYHR: Weekday and Hours Value Register(1)

      297
    • Register 24-7: RTCVAL (When RTCPTR<1:0> = 00): Minutes and SEconds Value Register

      297
    • Register 24-8: ALRMVAL (When ALRMPTR<1:0> = 10): Alarm Month and Day Value Register(1)

      298
    • Register 24-9: ALRMVAL (When ALRMPTR<1:0> = 01): Alarm Weekday and Hours Value Register(1)

      298
    • Register 24-10: ALRMVAL (When ALRMPTR<1:0> = 00): Alarm Minutes and Seconds Value Register

      299
• 25.0 Programmable Cyclic Redundancy Check (CRC) Generator

  301
  • 25.1 Overview

    301
    • EQUATION 25-1: CRC equation

      301
    • TABLE 25-1: Example CRC Setup

      301
    • FIGURE 25-1: CRC Shifter Details

      301
    • FIGURE 25-2: CRC Generator Reconfigured for x16 + x12 + x5 + 1

      302
  • 25.2 User Interface

    302
  • 25.3 Operation in Power-Saving Modes

    302
  • 25.4 Programmable CRC Resources

    303
  • 25.5 Programmable CRC Registers

    304
    • Register 25-1: CRCCON: CRC Control Register

      304
    • Register 25-2: CRCXOR: CRC XOR Polynomial Register

      305
• 26.0 Parallel Master Port (PMP)

  307
  • FIGURE 26-1: PMP Module Overview

    307
  • 26.1 PMP Resources

    308
  • 26.2 PMP Control Registers

    309
    • Register 26-1: PMCON: Parallel Master Port Control Register (Continued)

      309
    • Register 26-2: PMMODE: Parallel Port Mode Register

      311
    • Register 26-3: PMADDR: Parallel Port Address Register

      312
    • Register 26-4: PMAEN: Parallel Port Enable Register

      312
    • Register 26-5: PMSTAT: Parallel Port Status Register

      313
    • Register 26-6: PADCFG1: Pad Configuration Control Register

      314
• 27.0 Special Features

  315
  • 27.1 Configuration Bits

    315
    • TABLE 27-1: Device Configuration Register Map

      315
    • TABLE 27-2: dsPIC Configuration Bits Description (Continued)

      316
  • 27.2 On-Chip Voltage Regulator

    319
    • FIGURE 27-1: Connections for the On-Chip Voltage Regulator(1,2,3)

      319
  • 27.3 BOR: Brown-out Reset

    319
  • 27.4 Watchdog Timer (WDT)

    320
    • FIGURE 27-2: WDT Block Diagram

      320
  • 27.5 JTAG Interface

    321
  • 27.6 In-Circuit Serial Programming™ (ICSP)™

    321
  • 27.7 In-Circuit Debugger

    321
  • 27.8 Code Protection and CodeGuard™ Security

    321
    • TABLE 27-3: Code Flash Security Segment Sizes for 32 KB Devices

      322
    • TABLE 27-4: Code Flash Security Segment Sizes for 64 KB Devices

      323
    • TABLE 27-5: Code Flash Security Segment Sizes for 128 KB Devices

      324
• 28.0 Instruction Set Summary

  325
  • TABLE 28-1: Symbols used in Opcode Descriptions (Continued)

    326
  • TABLE 28-2: Instruction Set Overview (Continued)

    328
• 29.0 Development Support

  333
  • 29.1 MPLAB Integrated Development Environment Software

    333
  • 29.2 MPLAB C Compilers for Various Device Families

    334
  • 29.3 HI-TECH C for Various Device Families

    334
  • 29.4 MPASM Assembler

    334
  • 29.5 MPLINK Object Linker/ MPLIB Object Librarian

    334
  • 29.6 MPLAB Assembler, Linker and Librarian for Various Device Families

    334
  • 29.7 MPLAB SIM Software Simulator

    335
  • 29.8 MPLAB REAL ICE In-Circuit Emulator System

    335
  • 29.9 MPLAB ICD 3 In-Circuit Debugger System

    335
  • 29.10 PICkit 3 In-Circuit Debugger/ Programmer and PICkit 3 Debug Express

    335
  • 29.11 PICkit 2 Development Programmer/Debugger and PICkit 2 Debug Express

    336
  • 29.12 MPLAB PM3 Device Programmer

    336
  • 29.13 Demonstration/Development Boards, Evaluation Kits, and Starter Kits

    336
• 30.0 Electrical Characteristics

  337
  • 30.1 DC Characteristics

    338
    • TABLE 30-1: Operating MIPS vs. Voltage

      338
    • TABLE 30-2: Thermal Operating Conditions

      338
    • TABLE 30-3: Thermal Packaging Characteristics

      338
    • TABLE 30-4: DC Temperature and Voltage specifications

      339
    • TABLE 30-5: DC Characteristics: Operating Current (Idd)

      340
    • TABLE 30-6: DC Characteristics: Idle Current (Iidle)

      341
    • TABLE 30-7: DC Characteristics: Power-Down Current (Ipd)

      342
    • TABLE 30-8: DC Characteristics: Doze Current (Idoze)

      343
    • TABLE 30-9: DC Characteristics: I/O Pin Input Specifications (Continued)

      344
    • TABLE 30-10: DC Characteristics: I/O Pin Output Specifications

      347
    • TABLE 30-11: Electrical Characteristics: BOR

      348
    • TABLE 30-12: DC Characteristics: Program Memory

      348
    • TABLE 30-13: Internal Voltage Regulator Specifications

      348
  • 30.2 AC Characteristics and Timing Parameters

    349
    • TABLE 30-14: Temperature and Voltage Specifications – AC

      349
    • FIGURE 30-1: Load Conditions for Device Timing Specifications

      349
    • TABLE 30-15: Capacitive Loading Requirements on Output Pins

      349
    • FIGURE 30-2: External Clock Timing

      350
    • TABLE 30-16: External Clock Timing Requirements

      350
    • TABLE 30-17: PLL Clock Timing Specifications (Vdd = 3.0V to 3.6V)

      351
    • TABLE 30-18: AC Characteristics: Internal RC Accuracy

      351
    • TABLE 30-19: Internal RC accuracy

      351
    • FIGURE 30-3: CLKO and I/O Timing Characteristics

      352
    • TABLE 30-20: I/O Timing Requirements

      352
    • FIGURE 30-4: Reset, Watchdog Timer, Oscillator Start-up Timer and Power-up Timer Timing Characteristics

      353
    • TABLE 30-21: Reset, Watchdog Timer, Oscillator Start-up Timer, Power-up Timer Timing Requirements

      354
    • FIGURE 30-5: Timer1, 2, 3 and 4 External Clock Timing Characteristics

      355
    • TABLE 30-22: Timer1 External Clock Timing Requirements(1)

      355
    • TABLE 30-23: Timer2 and Timer 4 External Clock Timing Requirements

      356
    • TABLE 30-24: Timer3 and Timer5 External Clock Timing Requirements

      356
    • FIGURE 30-6: Input Capture (CAPx) Timing Characteristics

      357
    • TABLE 30-25: Input Capture Timing Requirements

      357
    • FIGURE 30-7: Output Compare Module (OCx) Timing Characteristics

      357
    • TABLE 30-26: Output Compare Module Timing Requirements

      357
    • FIGURE 30-8: OC/PWM Module Timing Characteristics

      358
    • TABLE 30-27: Simple OC/PWM MODE Timing Requirements

      358
    • TABLE 30-28: SPIx Maximum Data/CLock Rate Summary

      359
    • FIGURE 30-9: SPIx MASTER MODE (Half-Duplex, Transmit Only CKE = 0) TIMING CHARACTERISTICS

      359
    • FIGURE 30-10: SPIx MASTER MODE (Half-Duplex, Transmit Only CKE = 1) TIMING CHARACTERISTICS

      359
    • TABLE 30-29: SPIx Master Mode (Half-Duplex, Transmit Only) Timing Requirements

      360
    • FIGURE 30-11: SPIx MASTER MODE (Full-Duplex, CKE = 1, CKP = X, SMP = 1) TIMING CHARACTERISTICS

      361
    • TABLE 30-30: SPIx Master Mode (Full-Duplex, CKE = 1, CKP = x, SMP = 1) Timing Requirements

      361
    • FIGURE 30-12: SPIx MASTER MODE (Full-Duplex, CKE = 0, CKP = X, SMP = 1) TIMING CHARACTERISTICS

      362
    • TABLE 30-31: SPIx Master Mode (Full-Duplex, CKE = 0, CKP = x, SMP = 1) Timing Requirements

      362
    • FIGURE 30-13: SPIx SLAVE MODE (Full-Duplex, CKE = 1, CKP = 0, SMP = 0) TIMING CHARACTERISTICS

      363
    • TABLE 30-32: SPIx Slave Mode (Full-Duplex, CKE = 1, CKP = 0, SMP = 0) Timing Requirements

      364
    • FIGURE 30-14: SPIx SLAVE MODE (Full-Duplex, CKE = 1, CKP = 1, SMP = 0) TIMING CHARACTERISTICS

      365
    • TABLE 30-33: SPIx Slave Mode (Full-Duplex, CKE = 1, CKP = 1, SMP = 0) Timing Requirements

      366
    • FIGURE 30-15: SPIx SLAVE MODE (Full-Duplex CKE = 0, CKP = 1, SMP = 0) TIMING CHARACTERISTICS

      367
    • TABLE 30-34: SPIx Slave Mode (Full-Duplex, CKE = 0, CKP = 1, SMP = 0) Timing Requirements

      368
    • FIGURE 30-16: SPIx SLAVE MODE (Full-Duplex, CKE = 0, CKP = 0, SMP = 0) TIMING CHARACTERISTICS

      369
    • TABLE 30-35: SPIx Slave Mode (Full-Duplex, CKE = 0, CKP = 0, SMP = 0) Timing Requirements

      370
    • FIGURE 30-17: I2Cx Bus Start/Stop Bits Timing Characteristics (Master Mode)

      371
    • FIGURE 30-18: I2Cx Bus Data Timing Characteristics (Master Mode)

      371
    • TABLE 30-36: I2Cx Bus Data Timing Requirements (Master Mode)

      372
    • FIGURE 30-19: I2Cx Bus Start/Stop Bits Timing Characteristics (Slave Mode)

      373
    • FIGURE 30-20: I2Cx Bus Data Timing Characteristics (Slave Mode)

      373
    • TABLE 30-37: I2Cx Bus Data Timing Requirements (Slave Mode)

      374
    • FIGURE 30-21: DCI Module (Multi-Channel, I2S Modes) Timing Characteristics

      375
    • TABLE 30-38: DCI Module (Multi-Channel, I2S Modes) Timing Requirements

      376
    • FIGURE 30-22: DCI Module (AC-Link Mode) Timing Characteristics

      377
    • TABLE 30-39: DCI Module (AC-Link Mode) Timing Requirements

      378
    • FIGURE 30-23: ECAN™ Module I/O Timing Characteristics

      379
    • TABLE 30-40: ECAN™ Module I/O Timing Requirements

      379
    • TABLE 30-41: ADC Module Specifications

      380
    • TABLE 30-42: ADC Module Specifications (12-bit Mode)

      381
    • TABLE 30-43: ADC Module Specifications (10-bit Mode)

      382
    • FIGURE 30-24: ADC Conversion (12-bit Mode) Timing Characteristics (ASAM = 0, SSRC<2:0> = 000)

      383
    • TABLE 30-44: ADC Conversion (12-bit Mode) Timing Requirements

      384
    • FIGURE 30-25: ADC Conversion (10-bit Mode) Timing Characteristics (CHPS<1:0> = 01, SIMSAM = 0, ASAM = 0, SSRC<2:0> = 000)

      385
    • FIGURE 30-26: ADC Conversion (10-bit Mode) Timing Characteristics (CHPS<1:0> = 01, SIMSAM = 0, ASAM = 1, SSRC<2:0> = 111, SAMC<4:0> = 00001)

      385
    • TABLE 30-45: ADC Conversion (10-bit Mode) Timing Requirements

      386
    • TABLE 30-46: Audio DAC Module Specifications

      386
    • TABLE 30-47: Comparator Timing Specifications

      387
    • TABLE 30-48: Comparator Module Specifications

      387
    • TABLE 30-49: Comparator Reference Voltage Settling Time Specifications

      387
    • TABLE 30-50: Comparator Reference Voltage Specifications

      387
    • FIGURE 30-27: Parallel Slave Port Timing Diagram

      388
    • TABLE 30-51: Parallel Slave Port Time Specifications

      388
    • FIGURE 30-28: Parallel Master Port Read Timing Diagram

      389
    • TABLE 30-52: Parallel Master Port Read Timing Requirements

      389
    • FIGURE 30-29: Parallel Master Port Write Timing Diagram

      390
    • TABLE 30-53: Parallel Master Port Write Timing Requirements

      390
    • TABLE 30-54: DMA Read/Write Timing Requirements

      390
• 31.0 High Temperature Electrical Characteristics

  391
  • 31.1 High Temperature DC Characteristics

    392
    • TABLE 31-1: Operating MIPS vs. Voltage

      392
    • TABLE 31-2: Thermal Operating Conditions

      392
    • TABLE 31-3: DC Temperature and Voltage Specifications

      392
    • TABLE 31-4: DC Characteristics: Power-down Current (Ipd)

      393
    • TABLE 31-5: DC Characteristics: Doze Current (Idoze)

      393
    • TABLE 31-6: DC Characteristics: I/O Pin Output Specifications

      394
    • TABLE 31-7: DC Characteristics: Program Memory

      395
  • 31.2 AC Characteristics and Timing Parameters

    396
    • TABLE 31-8: Temperature and Voltage Specifications – AC

      396
    • FIGURE 31-1: Load Conditions for Device Timing Specifications

      396
    • TABLE 31-9: PLL Clock Timing Specifications

      396
    • TABLE 31-10: SPIx Master Mode (CKE = 0) Timing Requirements

      397
    • TABLE 31-11: SPIx Module Master Mode (CKE = 1) Timing Requirements

      397
    • TABLE 31-12: SPIx Module Slave Mode (CKE = 0) Timing Requirements

      398
    • TABLE 31-13: SPIx Module Slave Mode (CKE = 1) Timing Requirements

      398
    • TABLE 31-14: ADC Module Specifications

      399
    • TABLE 31-15: ADC Module Specifications (12-bit Mode)

      399
    • TABLE 31-16: ADC Module Specifications (10-bit Mode)

      400
    • TABLE 31-17: ADC Conversion (12-bit Mode) Timing Requirements

      401
    • TABLE 31-18: ADC Conversion (10-bit mode) Timing Requirements

      401
• 32.0 DC and AC Device Characteristics Graphs

  403
  • FIGURE 32-1: Voh – 2x Driver Pins

    403
  • FIGURE 32-2: Voh – 4x Driver Pins

    403
  • FIGURE 32-3: Voh – 8x Driver Pins

    403
  • FIGURE 32-4: Voh – 16x Driver Pins

    403
  • FIGURE 32-5: Vol – 2x Driver Pins

    404
  • FIGURE 32-6: Vol – 4x Driver Pins

    404
  • FIGURE 32-7: Vol – 8x Driver Pins

    404
  • FIGURE 32-8: Vol – 16x Driver Pins

    404
  • FIGURE 32-9: Typical Ipd Current @ Vdd = 3.3V, +85ºC

    405
  • FIGURE 32-10: Typical Idd Current @ Vdd = 3.3V, +85ºC

    405
  • FIGURE 32-11: Typical Idoze Current @ Vdd = 3.3V, +85ºC

    405
  • FIGURE 32-12: Typical Iidle Current @ Vdd = 3.3V, +85ºC

    405
  • FIGURE 32-13: Typical FRC Frequency @ Vdd = 3.3V

    406
  • FIGURE 32-14: Typical LPRC Frequency @ Vdd = 3.3V

    406
• 33.0 Packaging Information

  407
  • 33.1 Package Details

    408
• Appendix A: Revision History

  417
  • TABLE A-1: Major Section Updates

    417
  • TABLE A-2: Major Section Updates (Continued)

    418
  • TABLE A-3: Major Section Updates

    421
  • TABLE A-4: Major Section Updates (Continued)

    422
  • TABLE A-5: Major Section Updates

    425
  • TABLE A-6: Major Section Updates

    425
• INDEX

  427
• Worldwide Sales and Service

  436