Hoja De Datos (LAUNCHXL-TMS57004)Tabla de contenidos1 TMS570LS0432/0332 16- and 32-Bit RISC Flash Microcontroller11.1 Features11.2 Applications21.3 Description31.4 Functional Block Diagram5Table of Contents6Revision History72 Device Package and Terminal Functions82.1 PZ QFP Package Pinout (100-Pin)82.2 Terminal Functions92.2.1 High-End Timer (N2HET)102.2.2 Enhanced Quadrature Encoder Pulse Modules (eQEP)102.2.3 General-Purpose Input/Output (GIO)112.2.4 Controller Area Network Interface Modules (DCAN1, DCAN2)112.2.5 Multi-Buffered Serial Peripheral Interface (MibSPI1)112.2.6 Standard Serial Peripheral Interface (SPI2)122.2.7 Local Interconnect Network Controller (LIN)122.2.8 Multi-Buffered Analog-to-Digital Converter (MibADC)122.2.9 System Module132.2.10 Error Signaling Module (ESM)132.2.11 Main Oscillator142.2.12 Test/Debug Interface142.2.13 Flash142.2.14 Core Supply152.2.15 I/O Supply152.2.16 Core and I/O Supply Ground Reference152.3 Output Multiplexing and Control162.3.1 Notes on Output Multiplexing162.3.2 General Rules for Multiplexing Control Registers162.4 Special Multiplexed Options172.4.1 Filtering for eQEP Inputs172.4.1.1 eQEPA Input172.4.1.2 eQEPB Input172.4.1.3 eQEPI Input172.4.1.4 eQEPS Input172.4.2 N2HET PIN_nDISABLE Input Port173 Device Operating Conditions183.1 Absolute Maximum Ratings Over Operating Free-Air Temperature Range,183.2 Device Recommended Operating Conditions183.3 Switching Characteristics over Recommended Operating Conditions for Clock Domains193.4 Wait States Required193.5 Power Consumption Over Recommended Operating Conditions203.6 Input/Output Electrical Characteristics Over Recommended Operating Conditions213.7 Output Buffer Drive Strengths213.8 Input Timings223.9 Output Timings224 System Information and Electrical Specifications244.1 Voltage Monitor Characteristics244.1.1 Important Considerations244.1.2 Voltage Monitor Operation244.1.3 Supply Filtering244.2 Power Sequencing and Power On Reset254.2.1 Power-Up Sequence254.2.2 Power-Down Sequence264.2.3 Power-On Reset: nPORRST264.2.3.1 nPORRST Electrical and Timing Requirements264.3 Warm Reset (nRST)274.3.1 Causes of Warm Reset274.3.2 nRST Timing Requirements274.4 ARM© Cortex-R4™ CPU Information284.4.1 Summary of ARM Cortex-R4 CPU Features284.4.2 ARM Cortex-R4 CPU Features Enabled by Software284.4.3 Dual Core Implementation284.4.4 Duplicate clock tree after GCLK284.4.5 ARM Cortex-R4 CPU Compare Module (CCM) for Safety294.4.6 CPU Self-Test294.4.6.1 Application Sequence for CPU Self-Test294.4.6.2 CPU Self-Test Clock Configuration304.4.6.3 CPU Self-Test Coverage304.5 Clocks314.5.1 Clock Sources314.5.1.1 Main Oscillator314.5.1.2 Low Power Oscillator334.5.1.3 Phase Locked Loop (PLL) Clock Modules344.5.2 Clock Domains344.5.2.1 Clock Domain Descriptions344.5.2.2 Mapping of Clock Domains to Device Modules364.5.3 Clock Test Mode374.6 Clock Monitoring384.6.1 Clock Monitor Timings384.6.2 External Clock (ECLK) Output Functionality384.6.3 Dual Clock Comparator384.6.3.1 Features384.6.3.2 Mapping of DCC Clock Source Inputs394.7 Glitch Filters404.8 Device Memory Map414.8.1 Memory Map Diagram414.8.2 Memory Map Table434.8.3 Master/Slave Access Privileges464.9 Flash Memory474.9.1 Flash Memory Configuration474.9.2 Main Features of Flash Module474.9.3 ECC Protection for Flash Accesses484.9.4 Flash Access Speeds484.10 Flash Program and Erase Timings for Program Flash494.11 Flash Program and Erase Timings for Data Flash494.12 Tightly-Coupled RAM Interface Module504.12.1 Features504.12.2 TCRAMW ECC Support504.13 Parity Protection for Accesses to peripheral RAMs504.14 On-Chip SRAM Initialization and Testing524.14.1 On-Chip SRAM Self-Test Using PBIST524.14.1.1 Features524.14.1.2 PBIST RAM Groups524.14.2 On-Chip SRAM Auto Initialization534.15 Vectored Interrupt Manager544.15.1 VIM Features544.15.2 Interrupt Request Assignments544.16 Real Time Interrupt Module564.16.1 Features564.16.2 Block Diagrams564.16.3 Clock Source Options574.17 Error Signaling Module584.17.1 Features584.17.2 ESM Channel Assignments584.18 Reset / Abort / Error Sources624.19 Digital Windowed Watchdog634.20 Debug Subsystem644.20.1 Block Diagram644.20.2 Debug Components Memory Map644.20.3 JTAG Identification Code644.20.4 Debug ROM644.20.5 JTAG Scan Interface Timings654.20.6 Advanced JTAG Security Module664.20.7 Boundary Scan Chain675 Peripheral Information and Electrical Specifications685.1 Peripheral Legend685.2 Multi-Buffered 12-bit Analog-to-Digital Converter685.2.1 Features685.2.2 Event Trigger Options695.2.2.1 MIBADC Event Trigger Hookup695.2.3 ADC Electrical and Timing Specifications705.2.4 Performance (Accuracy) Specifications735.2.4.1 MibADC Nonlinearity Errors735.2.4.2 MibADC Total Error755.3 General-Purpose Input/Output765.3.1 Features765.4 Enhanced High-End Timer (N2HET)775.4.1 Features775.4.2 N2HET RAM Organization775.4.3 Input Timing Specifications775.4.4 N2HET Checking785.4.4.1 Output Monitoring using Dual Clock Comparator (DCC)785.4.5 Disabling N2HET Outputs785.4.6 High-End Timer Transfer Unit (N2HET)795.4.6.1 Features795.4.6.2 Trigger Connections795.5 Controller Area Network (DCAN)805.5.1 Features805.5.2 Electrical and Timing Specifications805.6 Local Interconnect Network Interface (LIN)815.6.1 LIN Features815.7 Multi-Buffered / Standard Serial Peripheral Interface825.7.1 Features825.7.2 MibSPI Transmit and Receive RAM Organization825.7.3 MibSPI Transmit Trigger Events825.7.3.1 MIBSPI1 Event Trigger Hookup835.7.4 MibSPI/SPI Master Mode I/O Timing Specifications845.7.5 SPI Slave Mode I/O Timings885.8 Enhanced Quadrature Encoder (eQEP)925.8.1 Clock Enable Control for eQEPx Modules925.8.2 Using eQEPx Phase Error925.8.3 Input Connections to eQEPx Modules925.8.4 Enhanced Quadrature Encoder Pulse (eQEPx) Timing936 Device and Documentation Support946.1 Device and Development-Support Tool Nomenclature946.2 Device Identification956.2.1 Device Identification Code Register956.2.2 Die Identification Registers976.3 Community Resources976.4 Module Certifications976.4.1 DCAN Certification986.4.2 LIN Certification996.4.2.1 LIN Master Mode996.4.2.2 LIN Slave Mode - Fixed Baud Rate1006.4.2.3 LIN Slave Mode - Adaptive Baud Rate1017 Mechanical Data1027.1 Thermal Data1027.2 Packaging Information102Tamaño: 8 MBPáginas: 106Language: EnglishManuales abiertas