Texas Instruments Hercules TMS570LS04x/03x LaunchPad Evaluation Kit LAUNCHXL-TMS57004 사용자 매뉴얼

차례

• 1 TMS570LS0432/0332 16- and 32-Bit RISC Flash Microcontroller

  1
  • 1.1 Features

    1
  • 1.2 Applications

    2
  • 1.3 Description

    3
  • 1.4 Functional Block Diagram

    5
• Table of Contents

  6
• Revision History

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• 2 Device Package and Terminal Functions

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  • 2.1 PZ QFP Package Pinout (100-Pin)

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  • 2.2 Terminal Functions

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    • 2.2.1 High-End Timer (N2HET)

      10
    • 2.2.2 Enhanced Quadrature Encoder Pulse Modules (eQEP)

      10
    • 2.2.3 General-Purpose Input/Output (GIO)

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    • 2.2.4 Controller Area Network Interface Modules (DCAN1, DCAN2)

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    • 2.2.5 Multi-Buffered Serial Peripheral Interface (MibSPI1)

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    • 2.2.6 Standard Serial Peripheral Interface (SPI2)

      12
    • 2.2.7 Local Interconnect Network Controller (LIN)

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    • 2.2.8 Multi-Buffered Analog-to-Digital Converter (MibADC)

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    • 2.2.9 System Module

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    • 2.2.10 Error Signaling Module (ESM)

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    • 2.2.11 Main Oscillator

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    • 2.2.12 Test/Debug Interface

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    • 2.2.13 Flash

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    • 2.2.14 Core Supply

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    • 2.2.15 I/O Supply

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    • 2.2.16 Core and I/O Supply Ground Reference

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  • 2.3 Output Multiplexing and Control

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    • 2.3.1 Notes on Output Multiplexing

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    • 2.3.2 General Rules for Multiplexing Control Registers

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  • 2.4 Special Multiplexed Options

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    • 2.4.1 Filtering for eQEP Inputs

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      • 2.4.1.1 eQEPA Input

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      • 2.4.1.2 eQEPB Input

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      • 2.4.1.3 eQEPI Input

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      • 2.4.1.4 eQEPS Input

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    • 2.4.2 N2HET PIN_nDISABLE Input Port

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• 3 Device Operating Conditions

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  • 3.1  Absolute Maximum Ratings Over Operating Free-Air Temperature Range,

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  • 3.2 Device Recommended Operating Conditions

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  • 3.3 Switching Characteristics over Recommended Operating Conditions for Clock Domains

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  • 3.4 Wait States Required

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  • 3.5 Power Consumption Over Recommended Operating Conditions

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  • 3.6 Input/Output Electrical Characteristics Over Recommended Operating Conditions

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  • 3.7 Output Buffer Drive Strengths

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  • 3.8 Input Timings

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  • 3.9 Output Timings

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• 4 System Information and Electrical Specifications

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  • 4.1 Voltage Monitor Characteristics

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    • 4.1.1 Important Considerations

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    • 4.1.2 Voltage Monitor Operation

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    • 4.1.3 Supply Filtering

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  • 4.2 Power Sequencing and Power On Reset

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    • 4.2.1 Power-Up Sequence

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    • 4.2.2 Power-Down Sequence

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    • 4.2.3 Power-On Reset: nPORRST

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      • 4.2.3.1 nPORRST Electrical and Timing Requirements

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  • 4.3 Warm Reset (nRST)

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    • 4.3.1 Causes of Warm Reset

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    • 4.3.2 nRST Timing Requirements

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  • 4.4 ARM© Cortex-R4™ CPU Information

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    • 4.4.1 Summary of ARM Cortex-R4 CPU Features

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    • 4.4.2 ARM Cortex-R4 CPU Features Enabled by Software

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    • 4.4.3 Dual Core Implementation

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    • 4.4.4 Duplicate clock tree after GCLK

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    • 4.4.5 ARM Cortex-R4 CPU Compare Module (CCM) for Safety

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    • 4.4.6 CPU Self-Test

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      • 4.4.6.1 Application Sequence for CPU Self-Test

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      • 4.4.6.2 CPU Self-Test Clock Configuration

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      • 4.4.6.3 CPU Self-Test Coverage

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  • 4.5 Clocks

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    • 4.5.1 Clock Sources

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      • 4.5.1.1 Main Oscillator

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      • 4.5.1.2 Low Power Oscillator

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      • 4.5.1.3 Phase Locked Loop (PLL) Clock Modules

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    • 4.5.2 Clock Domains

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      • 4.5.2.1 Clock Domain Descriptions

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      • 4.5.2.2 Mapping of Clock Domains to Device Modules

        36
    • 4.5.3 Clock Test Mode

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  • 4.6 Clock Monitoring

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    • 4.6.1 Clock Monitor Timings

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    • 4.6.2 External Clock (ECLK) Output Functionality

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    • 4.6.3 Dual Clock Comparator

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      • 4.6.3.1 Features

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      • 4.6.3.2 Mapping of DCC Clock Source Inputs

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  • 4.7 Glitch Filters

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  • 4.8 Device Memory Map

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    • 4.8.1 Memory Map Diagram

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    • 4.8.2 Memory Map Table

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    • 4.8.3 Master/Slave Access Privileges

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  • 4.9 Flash Memory

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    • 4.9.1 Flash Memory Configuration

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    • 4.9.2 Main Features of Flash Module

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    • 4.9.3 ECC Protection for Flash Accesses

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    • 4.9.4 Flash Access Speeds

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  • 4.10 Flash Program and Erase Timings for Program Flash

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  • 4.11 Flash Program and Erase Timings for Data Flash

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  • 4.12 Tightly-Coupled RAM Interface Module

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    • 4.12.1 Features

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    • 4.12.2 TCRAMW ECC Support

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  • 4.13  Parity Protection for Accesses to peripheral RAMs

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  • 4.14 On-Chip SRAM Initialization and Testing

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    • 4.14.1 On-Chip SRAM Self-Test Using PBIST

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      • 4.14.1.1 Features

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      • 4.14.1.2 PBIST RAM Groups

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    • 4.14.2 On-Chip SRAM Auto Initialization

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  • 4.15 Vectored Interrupt Manager

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    • 4.15.1 VIM Features

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    • 4.15.2 Interrupt Request Assignments

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  • 4.16 Real Time Interrupt Module

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    • 4.16.1 Features

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    • 4.16.2 Block Diagrams

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    • 4.16.3 Clock Source Options

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  • 4.17 Error Signaling Module

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    • 4.17.1 Features

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    • 4.17.2 ESM Channel Assignments

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  • 4.18 Reset / Abort / Error Sources

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  • 4.19 Digital Windowed Watchdog

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  • 4.20 Debug Subsystem

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    • 4.20.1 Block Diagram

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    • 4.20.2 Debug Components Memory Map

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    • 4.20.3 JTAG Identification Code

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    • 4.20.4 Debug ROM

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    • 4.20.5 JTAG Scan Interface Timings

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    • 4.20.6 Advanced JTAG Security Module

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    • 4.20.7 Boundary Scan Chain

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• 5 Peripheral Information and Electrical Specifications

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  • 5.1 Peripheral Legend

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  • 5.2 Multi-Buffered 12-bit Analog-to-Digital Converter

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    • 5.2.1 Features

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    • 5.2.2 Event Trigger Options

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      • 5.2.2.1 MIBADC Event Trigger Hookup

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    • 5.2.3 ADC Electrical and Timing Specifications

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    • 5.2.4 Performance (Accuracy) Specifications

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      • 5.2.4.1 MibADC Nonlinearity Errors

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      • 5.2.4.2 MibADC Total Error

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  • 5.3 General-Purpose Input/Output

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    • 5.3.1 Features

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  • 5.4 Enhanced High-End Timer (N2HET)

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    • 5.4.1 Features

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    • 5.4.2 N2HET RAM Organization

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    • 5.4.3 Input Timing Specifications

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    • 5.4.4 N2HET Checking

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      • 5.4.4.1 Output Monitoring using Dual Clock Comparator (DCC)

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    • 5.4.5 Disabling N2HET Outputs

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    • 5.4.6 High-End Timer Transfer Unit (N2HET)

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      • 5.4.6.1 Features

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      • 5.4.6.2 Trigger Connections

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  • 5.5 Controller Area Network (DCAN)

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    • 5.5.1 Features

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    • 5.5.2 Electrical and Timing Specifications

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  • 5.6 Local Interconnect Network Interface (LIN)

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    • 5.6.1 LIN Features

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  • 5.7 Multi-Buffered / Standard Serial Peripheral Interface

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    • 5.7.1 Features

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    • 5.7.2 MibSPI Transmit and Receive RAM Organization

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    • 5.7.3 MibSPI Transmit Trigger Events

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      • 5.7.3.1 MIBSPI1 Event Trigger Hookup

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    • 5.7.4 MibSPI/SPI Master Mode I/O Timing Specifications

      84
    • 5.7.5 SPI Slave Mode I/O Timings

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  • 5.8 Enhanced Quadrature Encoder (eQEP)

    92
    • 5.8.1 Clock Enable Control for eQEPx Modules

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    • 5.8.2 Using eQEPx Phase Error

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    • 5.8.3 Input Connections to eQEPx Modules

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    • 5.8.4 Enhanced Quadrature Encoder Pulse (eQEPx) Timing

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• 6 Device and Documentation Support

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  • 6.1 Device and Development-Support Tool Nomenclature

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  • 6.2 Device Identification

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    • 6.2.1 Device Identification Code Register

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    • 6.2.2 Die Identification Registers

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  • 6.3 Community Resources

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  • 6.4 Module Certifications

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    • 6.4.1 DCAN Certification

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    • 6.4.2 LIN Certification

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      • 6.4.2.1 LIN Master Mode

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      • 6.4.2.2 LIN Slave Mode - Fixed Baud Rate

        100
      • 6.4.2.3 LIN Slave Mode - Adaptive Baud Rate

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• 7 Mechanical Data

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  • 7.1 Thermal Data

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  • 7.2 Packaging Information

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