Intel SL2YM Manuel D’Utilisation
Pentium
®
II Processor at 350 MHz, 400 MHz, and 450 MHz
Datasheet
15
2.4.1
Processor V
CC
CORE
Decoupling
Regulator solutions need to provide bulk capacitance with a low Effective Series Resistance (ESR)
and keep an interconnect resistance from the regulator (or VRM pins) to the SC 242 connector of
less than 0.3 m
and keep an interconnect resistance from the regulator (or VRM pins) to the SC 242 connector of
less than 0.3 m
Ω
. This can be accomplished by keeping a maximum distance of 1.0 inches between
the regulator output and SC 242 connector. The recommended V
CC
CORE
interconnect is a 2.0 inch
wide (the width of the VRM 8.2 connector) by 1.0 inch long (maximum distance between the
SC 242 connector and the VRM 8.2 connector) plane segment with a 1-ounce plating. Bulk
decoupling for the large current swings when the part is powering on, or entering/exiting low
power states, is provided on the voltage regulation module (VRM). The V
SC 242 connector and the VRM 8.2 connector) plane segment with a 1-ounce plating. Bulk
decoupling for the large current swings when the part is powering on, or entering/exiting low
power states, is provided on the voltage regulation module (VRM). The V
CC
CORE
input should be
capable of delivering a recommended minimum dI
CC
CORE
/dt (defined in
Table 5
) while maintaining
the required tolerances (also defined in
Table 5
).
2.4.2
Processor System Bus AGTL+ Decoupling
The Pentium II processor contains high frequency decoupling capacitance on the processor
substrate; bulk decoupling must be provided for by the system motherboard for proper AGTL+ bus
operation. See AP-827, 100 MHz GTL+ Layout Guidelines for the Pentium
substrate; bulk decoupling must be provided for by the system motherboard for proper AGTL+ bus
operation. See AP-827, 100 MHz GTL+ Layout Guidelines for the Pentium
®
II Processor and
Intel
®
440BX AGPset (Order Number 243735), AP-587, Pentium
®
II Processor Power
Distribution Guidelines (Order Number 243332), and the Pentium
®
II Processor Developer's
Manual (Order Number 243502) for more information.
2.5
Processor System Bus Clock and Processor Clocking
The BCLK input directly controls the operating speed of the Pentium II processor system bus
interface. All Pentium II processor system bus timing parameters are specified with respect to the
rising edge of the BCLK input. See the Pentium
interface. All Pentium II processor system bus timing parameters are specified with respect to the
rising edge of the BCLK input. See the Pentium
®
II Processor Developer's Manual (Order Number
243502) for further details.
2.5.1
Mixing Processors of Different Frequencies
Mixing processors of different internal clock frequencies is not supported and has not been
validated by Intel. One should also note that when attempting to mix processors rated at different
frequencies in a two-way MP system, a common bus clock frequency and a set of multipliers must
be found that is acceptable to both processors in the system. A processor may run at a core
frequency as low as its minimum rating.
validated by Intel. One should also note that when attempting to mix processors rated at different
frequencies in a two-way MP system, a common bus clock frequency and a set of multipliers must
be found that is acceptable to both processors in the system. A processor may run at a core
frequency as low as its minimum rating.
2.6
Voltage Identification
There are five voltage identification pins on the SC 242 connector. These pins can be used to
support automatic selection of power supply voltages. These pins are not signals, but are either an
open circuit or a short circuit to V
support automatic selection of power supply voltages. These pins are not signals, but are either an
open circuit or a short circuit to V
SS
on the processor. The combination of opens and shorts defines
the voltage required by the processor core. The VID pins are needed to cleanly support voltage
specification variations on current and future Pentium II processors. These pins (VID[0] through
VID[4]) are defined in
specification variations on current and future Pentium II processors. These pins (VID[0] through
VID[4]) are defined in
Table 1
. A ‘1’ in this table refers to an open pin and a ‘0’ refers to a short to
ground. The definition provided in
Table 1
is a superset of the definition previously defined for the
Pentium Pro processor. The power supply must supply the voltage that is requested or disable
itself.
itself.