Hynix HMP125U6EFR8C-S6 Fascicule
Rev. 0.3 / Nov. 2008 12
1
240pin DDR2 SDRAM Unbuffered DIMMs
INPUT DC LOGIC LEVEL
INPUT AC LOGIC LEVEL
AC INPUT TEST CONDITIONS
Note:
1.
Input waveform timing is referenced to the input signal crossing through the V
REF
level applied to the device
under test.
2.
The input signal minimum slew rate is to be maintained over the range from V
REF
to V
IH(ac)
min for rising edges
and the range from V
REF
to V
IL(ac)
max for falling edges as shown in the below figure.
3.
AC timings are referenced with input waveforms switching from VIL (ac) to VIH (ac) on the positive transitions
and VIH (ac) to VIL (ac) on the negative transitions.
Parameter
Symbol
Min
Max
Unit
Note
dc Input logic HIGH
V
IH
(DC)
V
REF
+ 0.125
V
DDQ
+ 0.3
V
dc Input logic LOW
V
IL
(DC)
-0.30
V
REF
- 0.125
V
Parameter
Symbol
DDR2 400, 533
DDR2 667, 800
Unit
Note
Min
Max
Min
Max
AC Input logic High
V
IH
(AC)
V
REF
+ 0.250
-
V
REF
+ 0.200
-
V
AC Input logic Low
V
IL
(AC)
-
V
REF
- 0.250
-
V
REF
- 0.200
V
Symbol
Condition
Value
Units
Notes
V
REF
Input reference voltage
0.5 * V
DDQ
V
1
V
SWING(MAX)
Input signal maximum peak to peak swing
1.0
V
1
SLEW
Input signal minimum slew rate
1.0
V/ns
2, 3
V
DDQ
V
IH(ac)
min
V
IH(dc)
min
V
REF
V
IL(dc)
max
V
IL(ac)
max
V
SS
< Figure: AC Input Test Signal Waveform >
V
SWING(MAX)
delta TR
delta TF
V
REF
- V
IL(ac)
max
delta TF
Falling Slew =
Rising Slew =
V
IH(ac)
min - V
REF
delta TR