HP Intel Xeon W3530 WH059AV Manuel D’Utilisation

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Intel® Xeon® Processor 3500 Series Datasheet, Volume 2

This register provides SAD DRAM rules. Address Map for package determination.

This register provides SAD DRAM package assignments. When the corresponding 
DRAM_RULE hits, a 3-bit number (determined by mode) is used to index into the 
interleave_list to determine which package is the HOME for this address.

00: IOH
01: Socket 0
10: Socket 1
11: Reserved

19:6

RW

-

LIMIT 
DRAM rule top limit address. Must be strictly greater than previous rule, even if 

this rule is disabled, unless this rule and all following rules are disabled. Lower 

limit is the previous rule (or 0 if it is first rule). This field is compared against 

MA[39:26] in the memory address map.

2:1

RW

-

MODE 
DRAM rule interleave mode. If a DRAM_RULE hits a 3 bit number is used to 

index into the corresponding interleave_list to determine which package the 

DRAM belongs to. This mode selects how that number is computed. 
00 = Address bits {8,7,6}. 
01 = Address bits {8,7,6} XORed with {18,17,16}. 
10 = Address bit {6}, MOD3(Address[39..6]). (Note 6 is the high order bit) 
11 = Reserved.

0

RW

0

ENABLE 
Enable for DRAM rule. If Enabled Range between this rule and previous rule is 

Directed to HOME channel (unless overridden by other dedicated address range 

registers). If disabled, all accesses in this range are directed in MMIO to the 

IOH.

29:28

RW

-

PACKAGE7. Package for index value 7 of interleaves.

25:24

RW

-

PACKAGE6. Package for index value 6 of interleaves.

21:20

RW

-

PACKAGE5. Package for index value 5 of interleaves.