Fiche De Données (614740-001)Table des matières1 Introduction91.1 Terminology91.1.1 Processor Terminology101.2 References112 Electrical Specifications132.1 Power and Ground Lands132.2 Decoupling Guidelines132.2.1 VCC Decoupling132.2.2 Vtt Decoupling132.2.3 FSB Decoupling142.3 Voltage Identification142.4 Market Segment Identification (MSID)162.5 Reserved, Unused, and TESTHI Signals162.6 Voltage and Current Specification172.6.1 Absolute Maximum and Minimum Ratings172.6.2 DC Voltage and Current Specification182.6.3 VCC Overshoot222.6.4 Die Voltage Validation222.7 Signaling Specifications232.7.1 FSB Signal Groups232.7.2 CMOS and Open Drain Signals252.7.3 Processor DC Specifications252.7.4 Clock Specifications272.7.5 Front Side Bus Clock (BCLK[1:0]) and Processor Clocking272.7.6 FSB Frequency Select Signals (BSEL[2:0])282.7.7 Phase Lock Loop (PLL) and Filter282.7.8 BCLK[1:0] Specifications (CK505 based Platforms)292.7.9 BCLK[1:0] Specifications (CK410 based Platforms)302.8 PECI DC Specifications313 Package Mechanical Specifications333.1 Package Mechanical Drawing343.1.1 Processor Component Keep-Out Zones383.1.2 Package Loading Specifications383.1.3 Package Handling Guidelines383.1.4 Package Insertion Specifications383.1.5 Processor Mass Specification393.1.6 Processor Materials393.2 Processor Markings393.2.1 Processor Land Coordinates414 Land Listing and Signal Descriptions434.1 Processor Land Assignments434.2 Alphabetical Signals Reference665 Thermal Specifications and Design Considerations735.1 Processor Thermal Specifications735.1.1 Thermal Specifications735.1.2 Thermal Metrology785.2 Processor Thermal Features785.2.1 Thermal Monitor785.2.2 Thermal Monitor 2795.2.3 On-Demand Mode805.2.4 PROCHOT# Signal815.2.5 THERMTRIP# Signal815.3 Thermal Diode815.4 Platform Environment Control Interface (PECI)835.4.1 Introduction835.4.2 PECI Specifications866 Features876.1 Power-On Configuration Options876.2 Clock Control and Low Power States876.2.1 Normal State886.2.2 HALT and Extended HALT Powerdown States886.2.3 Stop Grant and Extended Stop Grant States896.2.4 Extended HALT Snoop State, HALT Snoop State, Extended Stop Grant Snoop State, and Stop Grant Snoop State906.3 Enhanced Intel® SpeedStep® Technology917 Boxed Processor Specifications937.1 Mechanical Specifications947.1.1 Boxed Processor Cooling Solution Dimensions947.1.2 Boxed Processor Fan Heatsink Weight957.1.3 Boxed Processor Retention Mechanism and Heatsink Attach Clip Assembly957.2 Electrical Requirements957.2.1 Fan Heatsink Power Supply957.3 Thermal Specifications977.3.1 Boxed Processor Cooling Requirements977.3.2 Variable Speed Fan998 Debug Tools Specifications1018.1 Logic Analyzer Interface (LAI)1018.1.1 Mechanical Considerations1018.1.2 Electrical Considerations101Taille: 2,4 MoPages: 102Language: EnglishOuvrir le manuel
Manuel D’Utilisation (WH059AV)Table des matières1 Introduction111.1 Terminology111.1.1 Processor Terminology111.2 References132 Register Description152.1 Register Terminology152.2 Platform Configuration Structure162.3 Device Mapping172.4 Detailed Configuration Space Maps182.5 PCI Standard Registers362.5.1 VID - Vendor Identification Register362.5.2 DID - Device Identification Register362.5.3 RID - Revision Identification Register372.5.4 CCR - Class Code Register372.5.5 HDR - Header Type Register382.5.6 SID/SVID - Subsystem Identity/Subsystem Vendor Identification Register382.5.7 PCICMD - Command Register392.5.8 PCISTS - PCI Status Register402.6 SAD - System Address Decoder Registers412.6.1 SAD_PAM0123412.6.2 SAD_PAM456432.6.3 SAD_HEN442.6.4 SAD_SMRAM442.6.5 SAD_PCIEXBAR452.6.6 SAD_DRAM_RULE_0, SAD_DRAM_RULE_1, SAD_DRAM_RULE_2, SAD_DRAM_RULE_3 SAD_DRAM_RULE_4, SAD_DRAM_RULE_5 SAD_DRAM_RULE_6, SAD_DRAM_RULE_7462.6.7 SAD_INTERLEAVE_LIST_0, SAD_INTERLEAVE_LIST_1 SAD_INTERLEAVE_LIST_2, SAD_INTERLEAVE_LIST_3 SAD_INTERLEAVE_LIST_4, SAD_INTERLEAVE_LIST_5 SAD_INTERLEAVE_LIST_6, SAD_INTERLEAVE_LIST_7462.7 Intel® QuickPath Interconnect Link Registers472.7.1 QPI_QPILCL_L0, QPI_QPILCL_L1472.8 Integrated Memory Controller Control Registers482.8.1 MC_CONTROL482.8.2 MC_STATUS492.8.3 MC_SMI_SPARE_DIMM_ERROR_STATUS502.8.4 MC_SMI_SPARE_CNTRL512.8.5 MC_RESET_CONTROL512.8.6 MC_CHANNEL_MAPPER522.8.7 MC_MAX_DOD532.8.8 MC_RD_CRDT_INIT542.8.9 MC_CRDT_WR_THLD552.8.10 MC_SCRUBADDR_LO552.8.11 MC_SCRUBADDR_HI562.9 TAD - Target Address Decoder Registers572.9.1 TAD_DRAM_RULE_0, TAD_DRAM_RULE_1 TAD_DRAM_RULE_2, TAD_DRAM_RULE_3 TAD_DRAM_RULE_4, TAD_DRAM_RULE_5 TAD_DRAM_RULE_6, TAD_DRAM_RULE_7572.9.2 TAD_INTERLEAVE_LIST_0, TAD_INTERLEAVE_LIST_1 TAD_INTERLEAVE_LIST_2, TAD_INTERLEAVE_LIST_3 TAD_INTERLEAVE_LIST_4, TAD_INTERLEAVE_LIST_5 TAD_INTERLEAVE_LIST_6, TAD_INTERLEAVE_LIST_7582.10 Integrated Memory Controller Channel Control Registers592.10.1 MC_CHANNEL_0_DIMM_RESET_CMD MC_CHANNEL_1_DIMM_RESET_CMD MC_CHANNEL_2_DIMM_RESET_CMD592.10.2 MC_CHANNEL_0_DIMM_INIT_CMD MC_CHANNEL_1_DIMM_INIT_CMD MC_CHANNEL_2_DIMM_INIT_CMD602.10.3 MC_CHANNEL_0_DIMM_INIT_PARAMS MC_CHANNEL_1_DIMM_INIT_PARAMS MC_CHANNEL_2_DIMM_INIT_PARAMS612.10.4 MC_CHANNEL_0_DIMM_INIT_STATUS MC_CHANNEL_1_DIMM_INIT_STATUS MC_CHANNEL_2_DIMM_INIT_STATUS622.10.5 MC_CHANNEL_0_DDR3CMD MC_CHANNEL_1_DDR3CMD MC_CHANNEL_2_DDR3CMD632.10.6 MC_CHANNEL_0_REFRESH_THROTTLE_SUPPORT MC_CHANNEL_1_REFRESH_THROTTLE_SUPPORT MC_CHANNEL_2_REFRESH_THROTTLE_SUPPORT642.10.7 MC_CHANNEL_0_MRS_VALUE_0_1 MC_CHANNEL_1_MRS_VALUE_0_1 MC_CHANNEL_2_MRS_VALUE_0_1642.10.8 MC_CHANNEL_0_MRS_VALUE_2 MC_CHANNEL_1_MRS_VALUE_2 MC_CHANNEL_2_MRS_VALUE_2652.10.9 MC_CHANNEL_0_RANK_PRESENT MC_CHANNEL_1_RANK_PRESENT MC_CHANNEL_2_RANK_PRESENT652.10.10 MC_CHANNEL_0_RANK_TIMING_A MC_CHANNEL_1_RANK_TIMING_A MC_CHANNEL_2_RANK_TIMING_A662.10.11 MC_CHANNEL_0_RANK_TIMING_B MC_CHANNEL_1_RANK_TIMING_B MC_CHANNEL_2_RANK_TIMING_B692.10.12 MC_CHANNEL_0_BANK_TIMING MC_CHANNEL_1_BANK_TIMING MC_CHANNEL_2_BANK_TIMING702.10.13 MC_CHANNEL_0_REFRESH_TIMING MC_CHANNEL_1_REFRESH_TIMING MC_CHANNEL_2_REFRESH_TIMING702.10.14 MC_CHANNEL_0_CKE_TIMING MC_CHANNEL_1_CKE_TIMING MC_CHANNEL_2_CKE_TIMING712.10.15 MC_CHANNEL_0_ZQ_TIMING MC_CHANNEL_1_ZQ_TIMING MC_CHANNEL_2_ZQ_TIMING712.10.16 MC_CHANNEL_0_RCOMP_PARAMS MC_CHANNEL_1_RCOMP_PARAMS MC_CHANNEL_2_RCOMP_PARAMS722.10.17 MC_CHANNEL_0_ODT_PARAMS1 MC_CHANNEL_1_ODT_PARAMS1 MC_CHANNEL_2_ODT_PARAMS1722.10.18 MC_CHANNEL_0_ODT_PARAMS2 MC_CHANNEL_1_ODT_PARAMS2 MC_CHANNEL_2_ODT_PARAMS2732.10.19 MC_CHANNEL_0_ODT_MATRIX_RANK_0_3_RD MC_CHANNEL_1_ODT_MATRIX_RANK_0_3_RD MC_CHANNEL_2_ODT_MATRIX_RANK_0_3_RD732.10.20 MC_CHANNEL_0_ODT_MATRIX_RANK_4_7_RD MC_CHANNEL_1_ODT_MATRIX_RANK_4_7_RD MC_CHANNEL_2_ODT_MATRIX_RANK_4_7_RD742.10.21 MC_CHANNEL_0_ODT_MATRIX_RANK_0_3_WR MC_CHANNEL_1_ODT_MATRIX_RANK_0_3_WR MC_CHANNEL_2_ODT_MATRIX_RANK_0_3_WR742.10.22 MC_CHANNEL_0_ODT_MATRIX_RANK_4_7_WR MC_CHANNEL_1_ODT_MATRIX_RANK_4_7_WR MC_CHANNEL_2_ODT_MATRIX_RANK_4_7_WR742.10.23 MC_CHANNEL_0_WAQ_PARAMS MC_CHANNEL_1_WAQ_PARAMS MC_CHANNEL_2_WAQ_PARAMS752.10.24 MC_CHANNEL_0_SCHEDULER_PARAMS MC_CHANNEL_1_SCHEDULER_PARAMS MC_CHANNEL_2_SCHEDULER_PARAMS762.10.25 MC_CHANNEL_0_MAINTENANCE_OPS MC_CHANNEL_1_MAINTENANCE_OPS MC_CHANNEL_2_MAINTENANCE_OPS762.10.26 MC_CHANNEL_0_TX_BG_SETTINGS MC_CHANNEL_1_TX_BG_SETTINGS MC_CHANNEL_2_TX_BG_SETTINGS772.10.27 MC_CHANNEL_0_RX_BGF_SETTINGS MC_CHANNEL_1_RX_BGF_SETTINGS MC_CHANNEL_2_RX_BGF_SETTINGS772.10.28 MC_CHANNEL_0_EW_BGF_SETTINGS MC_CHANNEL_1_EW_BGF_SETTINGS MC_CHANNEL_2_EW_BGF_SETTINGS782.10.29 MC_CHANNEL_0_EW_BGF_OFFSET_SETTINGS MC_CHANNEL_1_EW_BGF_OFFSET_SETTINGS MC_CHANNEL_2_EW_BGF_OFFSET_SETTINGS782.10.30 MC_CHANNEL_0_ROUND_TRIP_LATENCY MC_CHANNEL_1_ROUND_TRIP_LATENCY MC_CHANNEL_2_ROUND_TRIP_LATENCY782.10.31 MC_CHANNEL_0_PAGETABLE_PARAMS1 MC_CHANNEL_1_PAGETABLE_PARAMS1 MC_CHANNEL_2_PAGETABLE_PARAMS1792.10.32 MC_CHANNEL_0_PAGETABLE_PARAMS2 MC_CHANNEL_1_PAGETABLE_PARAMS2 MC_CHANNEL_2_PAGETABLE_PARAMS2792.10.33 MC_TX_BG_CMD_DATA_RATIO_SETTINGS_CH0 MC_TX_BG_CMD_DATA_RATIO_SETTINGS_CH1 MC_TX_BG_CMD_DATA_RATIO_SETTINGS_CH2802.10.34 MC_TX_BG_CMD_OFFSET_SETTINGS_CH0 MC_TX_BG_CMD_OFFSET_SETTINGS_CH1 MC_TX_BG_CMD_OFFSET_SETTINGS_CH2802.10.35 MC_TX_BG_DATA_OFFSET_SETTINGS_CH0 MC_TX_BG_DATA_OFFSET_SETTINGS_CH1 MC_TX_BG_DATA_OFFSET_SETTINGS_CH2802.10.36 MC_CHANNEL_0_ADDR_MATCH MC_CHANNEL_1_ADDR_MATCH MC_CHANNEL_2_ADDR_MATCH812.10.37 MC_CHANNEL_0_ECC_ERROR_MASK MC_CHANNEL_1_ECC_ERROR_MASK MC_CHANNEL_2_ECC_ERROR_MASK822.10.38 MC_CHANNEL_0_ECC_ERROR_INJECT MC_CHANNEL_1_ECC_ERROR_INJECT MC_CHANNEL_2_ECC_ERROR_INJECT822.10.39 Error Injection Implementation832.11 Integrated Memory Controller Channel Address Registers842.11.1 MC_DOD_CH0_0, MC_DOD_CH0_1, MC_DOD_CH0_2842.11.2 MC_DOD_CH1_0, MC_DOD_CH1_1, MC_DOD_CH1_2852.11.3 MC_DOD_CH2_0, MC_DOD_CH2_1, MC_DOD_CH2_2862.11.4 MC_SAG_CH0_0, MC_SAG_CH0_1, MC_SAG_CH0_2 MC_SAG_CH0_3, MC_SAG_CH0_4, MC_SAG_CH0_5 MC_SAG_CH0_6, MC_SAG_CH0_7, MC_SAG_CH1_...872.12 Integrated Memory Controller Channel Rank Registers882.12.1 MC_RIR_LIMIT_CH0_0, MC_RIR_LIMIT_CH0_1 MC_RIR_LIMIT_CH0_2, MC_RIR_LIMIT_CH0_3 MC_RIR_LIMIT_CH0_4, MC_RIR_LIMIT_CH0_5 MC_R...882.12.2 MC_RIR_WAY_CH0_0, MC_RIR_WAY_CH0_1 MC_RIR_WAY_CH0_2, MC_RIR_WAY_CH0_3 MC_RIR_WAY_CH0_4, MC_RIR_WAY_CH0_5 MC_RIR_WAY_CH0_6...892.12.3 MC_RIR_WAY_CH1_0, MC_RIR_WAY_CH1_1 MC_RIR_WAY_CH1_2, MC_RIR_WAY_CH1_3 MC_RIR_WAY_CH1_4, MC_RIR_WAY_CH1_5 MC_RIR_WAY_CH1_6...902.12.4 MC_RIR_WAY_CH2_0, MC_RIR_WAY_CH2_1 MC_RIR_WAY_CH2_2, MC_RIR_WAY_CH2_3 MC_RIR_WAY_CH2_4, MC_RIR_WAY_CH2_5 MC_RIR_WAY_CH2_6...912.13 Memory Thermal Control922.13.1 MC_THERMAL_CONTROL0 MC_THERMAL_CONTROL1 MC_THERMAL_CONTROL2922.13.2 MC_THERMAL_STATUS0 MC_THERMAL_STATUS1 MC_THERMAL_STATUS2922.13.3 MC_THERMAL_DEFEATURE0 MC_THERMAL_DEFEATURE1 MC_THERMAL_DEFEATURE2932.13.4 MC_THERMAL_PARAMS_A0 MC_THERMAL_PARAMS_A1 MC_THERMAL_PARAMS_A2932.13.5 MC_THERMAL_PARAMS_B0 MC_THERMAL_PARAMS_B1 MC_THERMAL_PARAMS_B2942.13.6 MC_COOLING_COEF0 MC_COOLING_COEF1 MC_COOLING_COEF2942.13.7 MC_CLOSED_LOOP0 MC_CLOSED_LOOP1 MC_CLOSED_LOOP2952.13.8 MC_THROTTLE_OFFSET0 MC_THROTTLE_OFFSET1 MC_THROTTLE_OFFSET2952.13.9 MC_RANK_VIRTUAL_TEMP0 MC_RANK_VIRTUAL_TEMP1 MC_RANK_VIRTUAL_TEMP2962.13.10 MC_DDR_THERM_COMMAND0 MC_DDR_THERM_COMMAND1 MC_DDR_THERM_COMMAND2962.13.11 MC_DDR_THERM_STATUS0 MC_DDR_THERM_STATUS1 MC_DDR_THERM_STATUS2972.14 Integrated Memory Controller Miscellaneous Registers972.14.1 MC_DIMM_CLK_RATIO_STATUS972.14.2 MC_DIMM_CLK_RATIO98Taille: 1,2 MoPages: 98Language: EnglishOuvrir le manuel
