Emerson MVME2500 Manuel D’Utilisation
Functional Description
MVME2500 Installation and Use (6806800L01H)
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This section describes the protocol and interfaces provided in the QorIQ P20x0 integrated and
is utilized by the MVME2500.
is utilized by the MVME2500.
4.2.1
e500 Processor Core
The QorIQ integrated processors offer dual high performance e500v2 core (P2020) and a
single e500v2 core (P2010). It operates from 800 MHz up to 1.2GHz core frequency. The e500
processor core is a low-power implementation of the family of reduced instruction set
computing (RISC) embedded processor that implement the Book E definition of the PowerPC
architecture. The e500 is a 32-bit implementation of the Book E architecture using the lower
words of 64-bit general-purpose registers (GPRs) while E500v2 uses 36 bit physical addressing
and some improvement from the previous version.
single e500v2 core (P2010). It operates from 800 MHz up to 1.2GHz core frequency. The e500
processor core is a low-power implementation of the family of reduced instruction set
computing (RISC) embedded processor that implement the Book E definition of the PowerPC
architecture. The e500 is a 32-bit implementation of the Book E architecture using the lower
words of 64-bit general-purpose registers (GPRs) while E500v2 uses 36 bit physical addressing
and some improvement from the previous version.
4.2.2
Integrated Memory Controller
A fully programmable DDR SDRAM controller supports most JEDEC standard DDR2 and DDR3
memories available. Unbuffered registered DIMMs are also supported. A built-in error checking
and correction (ECC) ensures very low bit-error rates for reliable high-frequency operation.
Though ECC is not implemented on MVME2500, the board includes a place holder for
additional chips for ECC whenever it is needed in the future.
memories available. Unbuffered registered DIMMs are also supported. A built-in error checking
and correction (ECC) ensures very low bit-error rates for reliable high-frequency operation.
Though ECC is not implemented on MVME2500, the board includes a place holder for
additional chips for ECC whenever it is needed in the future.
The memory controller supports the following:
16 GB of memory
Asynchronous clocking from platform clock, with programmable settings that meets all
the SDRAM timing parameters.
the SDRAM timing parameters.
Up to four physical banks; each bank can be independently addressed to 64 Mbit to 4 Gbit
memory devices (depending on the internal device configuration with x8/x16/x32 data
ports).
memory devices (depending on the internal device configuration with x8/x16/x32 data
ports).
Chip set interleaving and partial array self-refresh.
Data mask signal and read-modify-write for sub-double-word writes when ECC is enabled.
Double-bit error detection and single-bit error correction ECC, 8-bit check work across 64-
bit data.
bit data.
Address parity for registered DIMMs.