Intel 413808 Manuel D’Utilisation

Intel

413808 and 413812 I/O Controllers in TPER Mode

October 2007

Developer’s Manual

Order Number: 317805-001US

387

Address Translation Unit (PCI Express)—Intel

413808 and 413812

3.17.108 Inbound Vendor Message Header Register 3 - IVMHR3

Inbound Vendor Message Header Registers capture the header for a vendor defined

message received on the PCI Express interface. Once the inbound message is

processed, the Inbound Vendor Message Received bit is set in the

ATU Interrupt Status

. Subsequent inbound vendor messages are held in inbound posted

queues until the status bit is cleared or mask bit is set in the

ATU Interrupt Mask

. When mask bit is set, Vendor_Defined Type 0 messages are treated

as unsupported requests and Vendor_Defined Type 1 messages are silently discarded.

3.17.109 Inbound Vendor Message Payload Register - IVMPR

Inbound Vendor Message Payload Registers capture the payload for a vendor defined

message received on the PCI Express interface. Once the inbound message has been

processed, the Inbound Vendor Message Received bit is set in the

ATU Interrupt Status

. Subsequent inbound vendor messages are held in inbound posted

queues until the status bit is cleared or mask bit is set in the

ATU Interrupt Mask

. When the mask bit is set, Vendor_Defined Type 0 messages are

treated as unsupported requests and Vendor_Defined Type 1 messages are silently

discarded.

Table 248. Inbound Vendor Defined Message Header Register 3 - IVMHR3

Bit

Default

Description

31:24

00H

Header Byte 12

23:16

00H

Header Byte 13

15:8

00H

Header Byte 14

7:0

00H

Header Byte 15

PCI

IOP

Attributes

Attribute Legend:

RV = Reserved

PR = Preserved

RS = Read/Set

RW = Read/Write

RC = Read Clear

RO = Read Only

NA = Not Accessible

Internal Bus Address Offset

+34CH

Table 249. Inbound Vendor Defined Message Payload Register - IVMPR

Bit