Manuels d'utilisation pour Intel 413808

Table des matières

• Intel® 413808 and 413812 I/O Controllers in TPER Mode

  1
• 1.0 Introduction

  36
  • Table 1. Intel® 413808 and 413812 I/O Controllers in TPER Mode/Firmware Mapping

    36
  • Figure 1. TPER Architecture Overview

    37
  • 1.1 Design-in Considerations

    38
    • 1.1.1 Software

      39
  • 1.2 Documentation References

    40
    • Table 2. Documentation References

      40
  • 1.3 About This Document

    41
    • 1.3.1 How To Read This Document

      41
    • 1.3.2 Other Relevant Documents

      41
  • 1.4 About the Intel® 413808 and 413812 I/O Controllers in TPER Mode

    42
    • Figure 2. Intel® 413808 and 413812 I/O Controllers in TPER Mode Functional Block Diagram

      43
  • 1.5 Intel® 413808 and 413812 I/O Controllers in TPER Mode Features

    44
    • 1.5.1 Host Interface

      44
    • 1.5.2 Intel XScale® Processor

      44
    • 1.5.3 Internal Busses

      45
    • 1.5.4 Application DMA Controller

      45
    • 1.5.5 Address Translation Unit

      45
    • 1.5.6 Messaging Unit

      46
    • 1.5.7 DDR Memory Controller

      46
    • 1.5.8 Peripheral Bus Interface

      46
    • 1.5.9 Performance Monitoring Unit

      46
    • 1.5.10 I2C Bus Interface Unit

      46
    • 1.5.11 UART Unit

      46
    • 1.5.12 Interrupt Controller Unit

      46
    • 1.5.13 Internal Bus System Controller

      47
    • 1.5.14 Inter-Processor Communication

      47
    • 1.5.15 Inter-Processor Messaging Unit

      47
    • 1.5.16 Timers

      47
    • 1.5.17 GPIO

      47
    • 1.5.18 FSENG

      47
  • 1.6 Terminology and Conventions

    48
    • 1.6.1 Representing Numbers

      48
    • 1.6.2 Fields

      48
    • 1.6.3 Specifying Bit and Signal Values

      49
    • 1.6.4 Signal Name Conventions

      49
    • 1.6.5 Terminology

      49
• 2.0 Address Translation Unit (PCI-X)

  50
  • 2.1 Overview

    50
    • Figure 3. ATU Block Diagram

      51
    • Figure 4. ATU Queue Architecture Block Diagram

      52
  • 2.2 ATU Address Translation

    53
    • Table 3. ATU Command Support

      54
    • 2.2.1 Inbound Transactions

      55
      • 2.2.1.1 Inbound Address Translation

        56
        • Equation 1. Inbound Address Detection

          56
        • Figure 5. Inbound Address Detection

          57
        • Equation 2. Inbound Translation

          57
        • Figure 6. Inbound Translation Example

          58
      • 2.2.1.2 Inbound Write Transaction

        59
      • 2.2.1.3 Inbound Read Transaction

        61
      • 2.2.1.4 Inbound Configuration Cycle Translation

        64
      • 2.2.1.5 Discard Timers

        66
    • 2.2.2 Outbound Transactions- Single Address Cycle (SAC) Internal Bus Transactions

      67
      • 2.2.2.1 Outbound Address Translation - Internal Bus Transactions

        68
        • Figure 7. 4 Gbyte Section 0 of the Internal Bus Memory Map

          68
        • Table 4. Outbound Address Translation Control

          68
      • 2.2.2.2 Outbound Address Translation Windows

        69
        • Figure 8. Outbound Address Translation Windows

          69
        • Table 5. Internal Bus-to-PCI Command Translation for Memory Windows

          70
        • Table 6. Internal Bus-to-PCI Command Translation for I/O Window

          70
        • Equation 3. Outbound Address Translation

          71
        • Equation 4. I/O Transactions

          71
    • 2.2.3 Outbound Write Transaction

      72
    • 2.2.4 Outbound Read Transaction

      74
    • 2.2.5 Outbound Configuration Cycle Translation

      75
      • 2.2.5.1 PCI-X Mode 1 Considerations for Outbound Configuration Cycles

        75
      • 2.2.5.2 PCI-X Mode 2 Considerations for Outbound Configuration Cycles

        76
      • 2.2.5.3 Outbound Configuration Cycle Error Conditions

        76
    • 2.2.6 Internal Bus Operation

      77
  • 2.3 Big Endian Byte Swapping

    78
    • 2.3.1 Inbound Byte Swapping

      78
      • Figure 9. Inbound Byte Swapping for 32-bit PCI

        78
      • Figure 10. Inbound Byte Swapping for 64-bit PCI

        78
    • 2.3.2 Outbound Byte Swapping

      79
      • Figure 11. Outbound Byte Swapping for Transaction with Byte Count of 1

        79
      • Figure 12. Outbound Byte Swapping for Transaction with Byte Count of 2

        79
      • Figure 13. Outbound Byte Swapping for Transaction with Byte Count of 3 or Larger

        79
  • 2.4 CompactPCI Hot-Swap

    80
    • 2.4.1 Pin Interface

      80
      • Table 7. Compact PCI Hot-Swap

        80
      • 2.4.1.1 Compact PCI Hot-Swap Mode Select

        81
        • Table 8. HS_FREQ Encoding

          81
  • 2.5 Expansion ROM Translation Unit

    82
  • 2.6 ATU Queue Architecture

    83
    • 2.6.1 Inbound Queues

      83
      • Table 9. Inbound Queues

        83
      • 2.6.1.1 Inbound Write Queue Structure

        83
      • 2.6.1.2 Inbound Read Queue Structure

        84
        • Table 10. Inbound Read Prefetch Data Sizes

          84
      • 2.6.1.3 Inbound Delayed Write Queue

        85
      • 2.6.1.4 Inbound Transaction Queues Command Translation Summary

        85
        • Table 11. PCI to Internal Bus Command Translation for All Inbound Transactions

          85
    • 2.6.2 Outbound Queues

      86
      • Table 12. Outbound Queues

        86
      • 2.6.2.1 Relaxed Ordering and No Snoop Outbound Request Attributes

        86
    • 2.6.3 Transaction Ordering

      87
      • Table 13. ATU Inbound Data Flow Ordering Rules

        87
      • Table 14. ATU Outbound Data Flow Ordering Rules

        88
      • 2.6.3.1 Transaction Ordering Summary

        90
        • Table 15. Inbound Transaction Ordering Summary

          90
        • Table 16. Outbound Transaction Ordering Summary

          91
    • 2.6.4 Byte Parity Checking and Generation

      92
      • 2.6.4.1 Parity Generation

        92
        • Equation 5. D_PARITY0 = D[0] XOR D[1] XOR D[2] XOR D[3] XOR D[4] XOR D[5] XOR D[6] XOR D[7] XOR WBE[0]

          92
        • Table 17. Parity Generation

          92
      • 2.6.4.2 Parity Checking

        93
        • Equation 6. PARITY_RESULT = A_PARITY0 XOR A[0] XOR A[1] XOR A[2] XOR A[3] XOR A[4] XOR A[5] XOR A[6] XOR A[7]

          93
        • Equation 7. PARITY_RESULT = D_PARITY0 XOR D[0] XOR D[1] XOR D[2] XOR D[3] XOR D[4] XOR D[5] XOR D[6] XOR D[7] XOR WBE[0]

          93
      • 2.6.4.3 Parity Disabled

        93
  • 2.7 ATU Error Conditions

    94
    • 2.7.1 Uncorrectable Address and Uncorrectable Attribute Errors on the PCI Interface

      95
    • 2.7.2 Correctable Address and Correctable Attribute Errors on the PCI Interface

      96
    • 2.7.3 Uncorrectable Data Errors on the PCI Interface

      97
      • 2.7.3.1 Outbound Read Request Uncorrectable Data Errors

        98
        • 2.7.3.1.1 Immediate Data Transfer

          98
        • 2.7.3.1.2 Split Response Termination

          99
      • 2.7.3.2 Outbound Write Request Uncorrectable Data Errors

        100
        • 2.7.3.2.1 Outbound Writes that are not MSI (Message Signaled Interrupts)

          100
        • 2.7.3.2.2 MSI Outbound Writes

          100
      • 2.7.3.3 Inbound Read Completions Uncorrectable Data Errors

        101
      • 2.7.3.4 Inbound Configuration Write Completion Message Uncorrectable Data Errors

        101
      • 2.7.3.5 Inbound Read Request Uncorrectable Data Errors

        101
        • 2.7.3.5.1 Immediate Data Transfer

          101
        • 2.7.3.5.2 Split Response Termination

          101
      • 2.7.3.6 Inbound Write Request Uncorrectable Data Errors

        101
      • 2.7.3.7 Outbound Read Completion Uncorrectable Data Errors

        102
      • 2.7.3.8 Outbound Split Write Uncorrectable Data Error Message

        103
      • 2.7.3.9 Inbound Configuration Write Request

        104
        • 2.7.3.9.1 Conventional PCI Mode

          104
        • 2.7.3.9.2 PCI-X Mode

          105
      • 2.7.3.10 Split Completion Messages

        106
    • 2.7.4 Correctable Data Errors on the PCI Interface

      107
      • 2.7.4.1 Inbound Read Request Correctable Data Errors

        107
        • 2.7.4.1.1 Immediate Data Transfer

          107
        • 2.7.4.1.2 Split Response Termination

          107
      • 2.7.4.2 Inbound Write Request Correctable Data Errors

        107
      • 2.7.4.3 Outbound Read Completion Correctable Data Errors

        108
      • 2.7.4.4 Inbound Configuration Write Request

        108
      • 2.7.4.5 Split Completion Messages

        108
    • 2.7.5 Master Aborts on the PCI Interface

      109
      • 2.7.5.1 Master Aborts for Outbound Read or Write Request

        109
      • 2.7.5.2 Inbound Read Completion or Inbound Configuration Write Completion Message

        110
      • 2.7.5.3 Master-Aborts Signaled by the ATU as a Target

        110
        • 2.7.5.3.1 Uncorrectable Address Errors

          110
        • 2.7.5.3.2 Internal Bus Master-Abort

          110
    • 2.7.6 Target Aborts on the PCI Interface

      111
      • 2.7.6.1 Target Aborts for Outbound Read Request or Outbound Write Request

        111
      • 2.7.6.2 Inbound Read Completion or Inbound Configuration Write Completion Message

        112
      • 2.7.6.3 Target-Aborts Signaled by the ATU as a Target

        112
        • 2.7.6.3.1 Internal Bus Master Abort

          112
        • 2.7.6.3.2 Internal Bus Target Abort

          112
        • 2.7.6.3.3 Inbound EROM Memory Write

          112
    • 2.7.7 Corrupted or Unexpected Split Completions

      113
      • 2.7.7.1 Completer Address

        113
      • 2.7.7.2 Completer Attributes

        113
    • 2.7.8 SERR# Assertion and Detection

      114
    • 2.7.9 Internal Bus Error Conditions

      115
      • 2.7.9.1 Master Abort on the Internal Bus

        115
        • 2.7.9.1.1 Inbound Write Request

          115
        • 2.7.9.1.2 Inbound Read Request

          116
      • 2.7.9.2 Target Abort on the Internal Bus

        117
        • 2.7.9.2.1 Conventional Mode

          117
        • 2.7.9.2.2 PCI-X Mode

          117
      • 2.7.9.3 Parity Error on the Internal Bus

        118
        • 2.7.9.3.1 Conventional Mode

          118
        • 2.7.9.3.2 PCI-X Mode

          118
    • 2.7.10 ATU Error Summary

      119
      • Table 18. ATU Error Reporting Summary - PCI Interface (Sheet 1 of 5)

        119
      • Table 19. ATU Error Reporting Summary - Internal Bus Interface

        124
  • 2.8 Message-Signaled Interrupts

    125
  • 2.9 Internal Interrupts

    126
  • 2.10 Vital Product Data

    127
    • 2.10.1 Configuring Vital Product Data Operation

      127
    • 2.10.2 Accessing Vital Product Data

      128
      • 2.10.2.1 Reading Vital Product Data

        128
      • 2.10.2.2 Writing Vital Product Data

        129
  • 2.11 Multi-Function Support

    130
    • 2.11.1 PCI-X Interface Control Parameters

      130
      • Table 20. PCI-X Interface Control Parameters Usage

        130
    • 2.11.2 PCI-X Interface Status Reporting

      131
      • Table 21. PCI-X Host Interface Status Reporting Usage

        131
  • 2.12 Central Resource Functionality

    132
    • 2.12.1 Multi-Function Support

      132
    • 2.12.2 Outbound Transactions

      132
    • 2.12.3 PCI Reset (P_RSTOUT#)

      132
    • 2.12.4 PCI Clock Outputs (P_CLKOUT, P_CLKO[3:0])

      132
    • 2.12.5 External Clock Driver (CR_FREQ[1:0])

      133
      • Table 22. CR_FREQ[1:0] Encoding

        133
    • 2.12.6 Bus Mode and Frequency Initialization

      134
      • Table 23. Device Mode/Frequency Capability Reporting

        134
      • Table 24. PCI Bus Frequency Initialization

        135
      • Table 25. PCI-X Initialization Pattern

        136
      • Figure 14. PCI-X Initialization Pattern Setting / Drive

        137
  • 2.13 Embedded Bridge Functionality

    138
  • 2.14 Register Definitions

    139
    • 2.14.1 PCI Configuration Registers

      139
      • Figure 15. ATU Interface Configuration Header Format

        139
      • Figure 16. ATU Interface Extended Configuration Header Format (Power Management)

        140
      • Figure 17. ATU Interface Extended Configuration Header Format (MSI-X Capability)

        140
      • Figure 18. ATU Interface Extended Configuration Header Format (MSI Capability)

        141
      • Figure 19. ATU Interface Extended Configuration Header Format (PCI-X Capability Type 1)

        141
      • Figure 20. ATU Extended Configuration Header Format (Compact PCI Hot-Swap Capability)

        142
      • Figure 21. ATU Interface Extended Configuration Header Format (VPD Capability)

        142
    • 2.14.2 Internal Bus Registers

      143
      • Table 26. Address Translation Unit Registers (Sheet 1 of 3)

        143
      • Table 27. ATU Internal Bus Memory Mapped Register Range Offsets

        146
      • Table 28. PCI-X Pad Registers

        146
    • 2.14.3 ATU Vendor ID Register - ATUVID

      147
      • Table 29. ATU Vendor ID Register - ATUVID

        147
    • 2.14.4 ATU Device ID Register - ATUDID

      147
      • Table 30. ATU Device ID Register - ATUDID

        147
    • 2.14.5 ATU Command Register - ATUCMD

      148
      • Table 31. ATU Command Register - ATUCMD

        148
    • 2.14.6 ATU Status Register - ATUSR

      149
      • Table 32. ATU Status Register - ATUSR (Sheet 1 of 2)

        149
    • 2.14.7 ATU Revision ID Register - ATURID

      151
      • Table 33. ATU Revision ID Register - ATURID

        151
    • 2.14.8 ATU Class Code Register - ATUCCR

      151
      • Table 34. ATU Class Code Register - ATUCCR

        151
    • 2.14.9 ATU Cacheline Size Register - ATUCLSR

      152
      • Table 35. ATU Cacheline Size Register - ATUCLSR

        152
    • 2.14.10 ATU Latency Timer Register - ATULT

      152
      • Table 36. ATU Latency Timer Register - ATULT

        152
    • 2.14.11 ATU Header Type Register - ATUHTR

      153
      • Table 37. ATU Header Type Register - ATUHTR

        153
    • 2.14.12 ATU BIST Register - ATUBISTR

      154
      • Table 38. ATU BIST Register - ATUBISTR

        154
    • 2.14.13 Inbound ATU Base Address Register 0 - IABAR0

      155
      • Table 39. Inbound ATU Base Address Register 0 - IABAR0

        155
    • 2.14.14 Inbound ATU Upper Base Address Register 0 - IAUBAR0

      156
      • Table 40. Inbound ATU Upper Base Address Register 0 - IAUBAR0

        156
    • 2.14.15 Inbound ATU Base Address Register 1 - IABAR1

      157
      • Table 41. Inbound ATU Base Address Register 1 - IABAR1

        157
    • 2.14.16 Inbound ATU Upper Base Address Register 1 - IAUBAR1

      158
      • Table 42. Inbound ATU Upper Base Address Register 1 - IAUBAR1

        158
    • 2.14.17 Inbound ATU Base Address Register 2 - IABAR2

      159
      • Table 43. Inbound ATU Base Address Register 2 - IABAR2

        159
    • 2.14.18 Inbound ATU Upper Base Address Register 2 - IAUBAR2

      160
      • Table 44. Inbound ATU Upper Base Address Register 2 - IAUBAR2

        160
    • 2.14.19 ATU Subsystem Vendor ID Register - ASVIR

      161
      • Table 45. ATU Subsystem Vendor ID Register - ASVIR

        161
    • 2.14.20 ATU Subsystem ID Register - ASIR

      161
      • Table 46. ATU Subsystem ID Register - ASIR

        161
    • 2.14.21 Expansion ROM Base Address Register - ERBAR

      162
      • Table 47. Expansion ROM Base Address Register -ERBAR

        162
    • 2.14.22 ATU Capabilities Pointer Register - ATU_Cap_Ptr

      163
      • Table 48. ATU Capabilities Pointer Register - ATU_Cap_Ptr

        163
    • 2.14.23 Determining Block Sizes for Base Address Registers

      164
      • Table 49. Memory Block Size Read Response

        164
      • Table 50. ATU Base Registers and Associated Limit Registers

        165
    • 2.14.24 ATU Interrupt Line Register - ATUILR

      166
      • Table 51. ATU Interrupt Line Register - ATUILR

        166
    • 2.14.25 ATU Interrupt Pin Register - ATUIPR

      167
      • Table 52. ATU Interrupt Pin Register - ATUIPR

        167
    • 2.14.26 ATU Minimum Grant Register - ATUMGNT

      167
      • Table 53. ATU Minimum Grant Register - ATUMGNT

        167
    • 2.14.27 ATU Maximum Latency Register - ATUMLAT

      168
      • Table 54. ATU Maximum Latency Register - ATUMLAT

        168
    • 2.14.28 Inbound ATU Limit Register 0 - IALR0

      169
      • Table 55. Inbound ATU Limit Register 0 - IALR0

        169
    • 2.14.29 Inbound ATU Translate Value Register 0 - IATVR0

      170
      • Table 56. Inbound ATU Translate Value Register 0 - IATVR0

        170
    • 2.14.30 Inbound ATU Upper Translate Value Register 0 - IAUTVR0

      170
      • Table 57. Inbound ATU Upper Translate Value Register 0 - IAUTVR0

        170
    • 2.14.31 Inbound ATU Limit Register 1 - IALR1

      171
      • Table 58. Inbound ATU Limit Register 1 - IALR1

        171
    • 2.14.32 Inbound ATU Translate Value Register 1 - IATVR1

      172
      • Table 59. Inbound ATU Translate Value Register 1 - IATVR1

        172
    • 2.14.33 Inbound ATU Upper Translate Value Register 1 - IAUTVR1

      172
      • Table 60. Inbound ATU Upper Translate Value Register 1 - IAUTVR1

        172
    • 2.14.34 Inbound ATU Limit Register 2 - IALR2

      173
      • Table 61. Inbound ATU Limit Register 2 - IALR2

        173
    • 2.14.35 Inbound ATU Translate Value Register 2 - IATVR2

      174
      • Table 62. Inbound ATU Translate Value Register 2 - IATVR2

        174
    • 2.14.36 Inbound ATU Upper Translate Value Register 2 - IAUTVR2

      174
      • Table 63. Inbound ATU Upper Translate Value Register 2 - IAUTVR2

        174
    • 2.14.37 Expansion ROM Limit Register - ERLR

      175
      • Table 64. Expansion ROM Limit Register - ERLR

        175
    • 2.14.38 Expansion ROM Translate Value Register - ERTVR

      176
      • Table 65. Expansion ROM Translate Value Register - ERTVR

        176
    • 2.14.39 Expansion ROM Upper Translate Value Register - ERUTVR

      176
      • Table 66. Expansion ROM Upper Translate Value Register - ERUTVR

        176
    • 2.14.40 ATU Configuration Register - ATUCR

      177
      • Table 67. ATU Configuration Register - ATUCR

        177
    • 2.14.41 PCI Configuration and Status Register - PCSR

      178
      • Table 68. PCI Configuration and Status Register - PCSR (Sheet 1 of 3)

        178
    • 2.14.42 ATU Interrupt Status Register - ATUISR

      181
      • Table 69. ATU Interrupt Status Register - ATUISR (Sheet 1 of 2)

        181
    • 2.14.43 ATU Interrupt Mask Register - ATUIMR

      183
      • Table 70. ATU Interrupt Mask Register - ATUIMR (Sheet 1 of 2)

        183
    • 2.14.44 VPD Capability Identifier Register - VPD_Cap_ID

      185
      • Table 71. VPD Capability Identifier Register - VPD_Cap_ID

        185
    • 2.14.45 VPD Next Item Pointer Register - VPD_Next_Item_Ptr

      185
      • Table 72. VPD Next Item Pointer Register - VPD_Next_Item_Ptr

        185
    • 2.14.46 VPD Address Register - VPDAR

      186
      • Table 73. VPD Address Register - VPDAR

        186
    • 2.14.47 VPD Data Register - VPDDR

      186
      • Table 74. VPD Data Register - VPDDR

        186
    • 2.14.48 PM Capability Identifier Register - PM_Cap_ID

      187
      • Table 75. PM_Capability Identifier Register - PM_Cap_ID

        187
    • 2.14.49 PM Next Item Pointer Register - PM_Next_Item_Ptr

      187
      • Table 76. PM Next Item Pointer Register - PM_Next_Item_Ptr

        187
    • 2.14.50 ATU Power Management Capabilities Register - APMCR

      188
      • Table 77. ATU Power Management Capabilities Register - APMCR

        188
    • 2.14.51 ATU Power Management Control/Status Register - APMCSR

      189
      • Table 78. ATU Power Management Control/Status Register - APMCSR

        189
    • 2.14.52 ATU Scratch Pad Register - ATUSPR

      190
      • Table 79. Scratch Pad Register - ATUSPR

        190
    • 2.14.53 PCI-X Capability Identifier Register - PCI-X_Cap_ID

      190
      • Table 80. PCI-X_Capability Identifier Register - PCI-X_Cap_ID

        190
    • 2.14.54 PCI-X Next Item Pointer Register - PCI-X_Next_Item_Ptr

      191
      • Table 81. PCI-X Next Item Pointer Register - PCI-X_Next_Item_Ptr

        191
    • 2.14.55 PCI-X Command Register - PCIXCMD

      191
      • Table 82. PCI-X Command Register - PCIXCMD (Sheet 1 of 2)

        191
    • 2.14.56 PCI-X Status Register - PCIXSR

      193
      • Table 83. PCI-X Status Register - PCIXSR (Sheet 1 of 2)

        193
    • 2.14.57 ECC Control and Status Register - ECCCSR

      195
      • Table 84. ECC Control and Status Register - ECCCSR (Sheet 1 of 3)

        195
    • 2.14.58 ECC First Address Register - ECCFAR

      198
      • Table 85. ECC First Address Register - ECCFAR

        198
    • 2.14.59 ECC Second Address Register - ECCSAR

      199
      • Table 86. ECC Second Address Register - ECCSAR

        199
    • 2.14.60 ECC Attribute Register - ECCAR

      200
      • Table 87. ECC Attribute Register - ECCAR

        200
    • 2.14.61 CompactPCI Hot-Swap Capability ID Register

      200
      • Table 88. HS_CAPID - Hot-Swap Cap ID

        200
    • 2.14.62 Offset EDh: HS_NXTP - Next Item Pointer

      201
      • Table 89. HS_NXTP - Next Item Pointer

        201
    • 2.14.63 HS_CNTRL - Hot-Swap Control/Status Register

      202
      • Table 90. HS_CNTRL - Hot-Swap Control/Status Register (Sheet 1 of 2)

        202
    • 2.14.64 Inbound ATU Base Address Register 3 - IABAR3

      204
      • Table 91. Inbound ATU Base Address Register 3 - IABAR3

        204
    • 2.14.65 Inbound ATU Upper Base Address Register 3 - IAUBAR3

      205
      • Table 92. Inbound ATU Upper Base Address Register 3 - IAUBAR3

        205
    • 2.14.66 Inbound ATU Limit Register 3 - IALR3

      206
      • Table 93. Inbound ATU Limit Register 3 - IALR3

        206
    • 2.14.67 Inbound ATU Translate Value Register 3 - IATVR3

      207
      • Table 94. Inbound ATU Translate Value Register 3 - IATVR3

        207
    • 2.14.68 Inbound ATU Upper Translate Value Register 3 - IAUTVR3

      207
      • Table 95. Inbound ATU Upper Translate Value Register 3 - IAUTVR3

        207
    • 2.14.69 Outbound I/O Base Address Register - OIOBAR

      208
      • Table 96. Outbound I/O Base Address Register - OIOBAR

        208
    • 2.14.70 Outbound I/O Window Translate Value Register - OIOWTVR

      209
      • Table 97. Outbound I/O Window Translate Value Register - OIOWTVR

        209
    • 2.14.71 Outbound Upper Memory Window Base Address Register 0 - OUMBAR0

      210
      • Table 98. Outbound Upper Memory Window Base Address Register 0 - OUMBAR0

        210
    • 2.14.72 Outbound Upper 32-bit Memory Window Translate Value Register 0 - OUMWTVR0

      211
      • Table 99. Outbound Upper 32-bit Memory Window Translate Value Register 0- OUMWTVR0

        211
    • 2.14.73 Outbound Upper Memory Window Base Address Register 1 - OUMBAR1

      212
      • Table 100. Outbound Upper Memory Window Base Address Register 1 - OUMBAR1

        212
    • 2.14.74 Outbound Upper 32-bit Memory Window Translate Value Register 1 - OUMWTVR1

      213
      • Table 101. Outbound Upper 32-bit Memory Window Translate Value Register 1- OUMWTVR1

        213
    • 2.14.75 Outbound Upper Memory Window Base Address Register 2 - OUMBAR2

      214
      • Table 102. Outbound Upper Memory Window Base Address Register 2- OUMBAR2

        214
    • 2.14.76 Outbound Upper 32-bit Memory Window Translate Value Register 2 - OUMWTVR2

      215
      • Table 103. Outbound Upper 32-bit Memory Window Translate Value Register 2- OUMWTVR2

        215
    • 2.14.77 Outbound Upper Memory Window Base Address Register 3 - OUMBAR3

      216
      • Table 104. Outbound Upper Memory Window Base Address Register 3 - OUMBAR3

        216
    • 2.14.78 Outbound Upper 32-bit Memory Window Translate Value Register 3 - OUMWTVR3

      217
      • Table 105. Outbound Upper 32-bit Memory Window Translate Value Register 3- OUMWTVR3

        217
    • 2.14.79 Outbound Configuration Cycle Address Register - OCCAR

      218
      • Table 106. Outbound Configuration Cycle Address Register - OCCAR

        218
    • 2.14.80 Outbound Configuration Cycle Data Register - OCCDR

      219
      • Table 107. Outbound Configuration Cycle Data Register - OCCDR

        219
    • 2.14.81 Outbound Configuration Cycle Function Number - OCCFN

      219
      • Table 108. Outbound Configuration Cycle Function Number Register - OCCFN

        219
    • 2.14.82 PCI Interface Error Control and Status Register - PIECSR

      220
      • Table 109. PCI Interface Error Control and Status Register - PIECSR

        220
    • 2.14.83 PCI Interface Error Address Register - PCIEAR

      221
      • Table 110. PCI Interface Error Address Register - PCIEAR

        221
    • 2.14.84 PCI Interface Error Upper Address Register - PCIEUAR

      222
      • Table 111. PCI Interface Error Upper Address Register - PCIEUAR

        222
    • 2.14.85 PCI Interface Error Context Address Register - PCIECAR

      223
      • Table 112. PCI Interface Error Context Address Register - PCIECAR

        223
    • 2.14.86 Internal Arbiter Control Register - IACR

      224
      • Table 113. Internal Arbiter Control Register - IACR

        224
    • 2.14.87 Multi-Transaction Timer - MTT

      225
      • Table 114. Multi-Transaction Timer - MTT

        225
    • 2.14.88 PCIX RCOMP Control Register - PRCR

      226
      • Table 115. PCIX RCOMP Control Register - PRCR

        226
    • 2.14.89 PCIX Pad ODT Drive Strength Manual Override Values Registers - PPODSMOVR

      227
      • Table 116. PCIX Pad ODT Drive Strength Manual Override Values Registers - PPODSMOVR

        227
    • 2.14.90 PCIX PAD DRIVE STRENGTH Manual Override Values Register (3.3 V/1.5 V Switch Supply Voltage) - PPDSMOVR3.3_1.5

      228
      • Table 117. PCIX PAD DRIVE STRENGTH Manual Override Values Register (3.3V/1.5V Switch Supply Voltage) - PPDSMOVR3.3_1.5

        228
    • 2.14.91 PCIX PAD DRIVE STRENGTH Manual Override Values Register (3.3 V Dedicated Supply Voltage) - PPDSMOVR3.3

      229
      • Table 118. PCIX PAD DRIVE STRENGTH Manual Override Values Register (3.3 V Dedicated Supply Voltage) - PPDSMOVR3.3

        229
• 3.0 Address Translation Unit (PCI Express)

  230
  • 3.1 Overview

    230
    • Figure 22. ATU Block Diagram

      231
    • Figure 23. ATU Queue Architecture Block Diagram

      232
  • 3.2 PCI Express Link Characteristics

    233
  • 3.3 ATU Address Translation

    234
    • Table 119. Supported Address Spaces and Transaction Types

      235
    • Table 120. ATU Command Support

      236
    • 3.3.1 Inbound Transactions

      237
      • 3.3.1.1 Inbound Address Translation

        237
        • Equation 8. Inbound Address Detection

          238
        • Figure 24. Inbound Address Detection

          238
        • Equation 9. Inbound Translation

          239
        • Figure 25. Inbound Translation Example

          239
      • 3.3.1.2 Inbound Memory Write Transaction

        240
      • 3.3.1.3 Inbound Memory Read Transaction

        241
      • 3.3.1.4 Inbound I/O Cycle Translation

        242
      • 3.3.1.5 Inbound Configuration Cycle Translation (ID Routed)

        242
      • 3.3.1.6 Inbound Vendor_Defined Message Transactions

        243
        • Table 121. Inbound Vendor_Defined Message Type 0 Response.

          243
    • 3.3.2 Outbound Transactions

      244
      • 3.3.2.1 Outbound Address Translation - Internal Bus Transactions

        245
        • Table 122. Outbound Address Translation Control

          245
      • 3.3.2.2 Outbound Address Translation Windows

        246
        • Table 123. Internal Bus-to-PCI Command Translation for Memory Windows

          246
        • Table 124. Internal Bus-to-PCI Command Translation for I/O Window

          246
        • Figure 26. 4 Gbyte Section 0 of the Internal Bus Memory Map

          247
        • Equation 10. Outbound Address Translation

          248
        • Equation 11. I/O Transactions

          248
        • Figure 27. Outbound Address Translation Windows

          249
      • 3.3.2.3 Outbound DMA Transactions

        250
      • 3.3.2.4 Outbound Function Number

        250
    • 3.3.3 Outbound Write Transaction

      251
    • 3.3.4 Outbound Read Transaction

      252
    • 3.3.5 Outbound Configuration Cycle Translation

      253
      • 3.3.5.1 Outbound Configuration Cycle Error Conditions

        253
      • 3.3.5.2 Outbound Configuration Completions with Retry Status (CRS)

        253
      • 3.3.5.3 Outbound PCI Express Message Transactions

        254
      • 3.3.5.4 Completion Timeout Mechanism

        254
  • 3.4 Big Endian Byte Swapping

    255
    • 3.4.1 Inbound Byte Swapping

      255
      • Figure 28. Inbound Byte Swapping

        255
    • 3.4.2 Outbound Byte Swapping

      256
      • Figure 29. Outbound Byte Swapping for Transaction with Byte Count of 1

        256
      • Figure 30. Outbound Byte Swapping for Transactions with Byte Count of 2

        256
      • Figure 31. Outbound Byte Swapping Transaction with Byte Count of 3 or Larger

        256
  • 3.5 Messaging Unit

    257
  • 3.6 PCI Express Messages

    258
    • Table 125. Supported Message Types (Sheet 1 of 2)

      258
  • 3.7 Expansion ROM Translation Unit

    260
  • 3.8 ATU Queue Architecture

    261
    • 3.8.1 Inbound Queues

      261
      • Table 126. Inbound Queues

        261
      • 3.8.1.1 Inbound Posted Queue Structure

        261
      • 3.8.1.2 Inbound Non Posted Queue Structure

        262
      • 3.8.1.3 Inbound Completion Queue Structure

        262
      • 3.8.1.4 Inbound Transaction Queues Command Translation Summary

        262
        • Table 127. PCI to Internal Bus Command Translation for All Inbound Transactions

          262
    • 3.8.2 Outbound Queues

      263
      • Table 128. Outbound Queues

        263
      • 3.8.2.1 Relaxed Ordering and No Snoop Outbound Request Attributes

        263
    • 3.8.3 Transaction Ordering

      264
      • Table 129. ATU Inbound Data Flow Ordering Rules

        264
      • Table 130. ATU Outbound Data Flow Ordering Rules

        265
      • 3.8.3.1 Transaction Ordering Summary

        267
        • Table 131. Inbound Transaction Ordering Summary

          267
        • Table 132. Outbound Transaction Ordering Summary

          267
    • 3.8.4 Byte Parity Checking and Generation

      268
      • 3.8.4.1 Parity Generation

        268
        • Equation 12. DATAP0 = D[0] XOR D[1] XOR D[2] XOR D[3] XOR D[4] XOR D[5] XOR D[6] XOR D[7] XOR WBE[0]

          268
        • Table 133. Parity Generation

          268
      • 3.8.4.2 Parity Checking

        269
        • Equation 13. PARITY_RESULT = ADDP0 XOR A[0] XOR A[1] XOR A[2] XOR A[3] XOR A[4] XOR A[5] XOR A[6] XOR A[7]

          269
        • Equation 14. PARITY_RESULT = DATAP0 XOR D[0] XOR D[1] XOR D[2] XOR D[3] XOR D[4] XOR D[5] XOR D[6] XOR D[7] XOR WBE[0]

          269
      • 3.8.4.3 Parity Disabled

        269
  • 3.9 ATU Error Conditions

    270
    • 3.9.1 PCI Express Errors

      271
      • 3.9.1.1 Role Based Error Reporting

        271
        • Table 134. Advisory Error Cases

          271
      • 3.9.1.2 Malformed Packets

        272
      • 3.9.1.3 ECRC Check Failed

        272
      • 3.9.1.4 Unsupported Request

        273
      • 3.9.1.5 Completer Abort

        273
      • 3.9.1.6 Unexpected Completions

        273
      • 3.9.1.7 Poisoned TLP Received

        274
      • 3.9.1.8 Completion Timeout

        274
    • 3.9.2 Parity Error on the Internal Bus

      275
    • 3.9.3 ATU Error Summary

      275
      • Table 135. PCI Express Error Summary (Sheet 1 of 2)

        276
      • Table 136. Root Complex Error Summary

        278
      • Table 137. Internal Bus Error Summary

        278
  • 3.10 PCI Express Hot-Plug Support

    279
  • 3.11 Reset

    280
  • 3.12 Message-Signaled Interrupts

    281
    • 3.12.1 Legacy Interrupts

      281
    • 3.12.2 Internal Interrupts

      281
  • 3.13 Vital Product Data

    282
    • 3.13.1 Configuring Vital Product Data Operation

      282
    • 3.13.2 Accessing Vital Product Data

      283
      • 3.13.2.1 Reading Vital Product Data

        283
      • 3.13.2.2 Writing Vital Product Data

        284
  • 3.14 Multi-Function Support

    285
    • 3.14.1 PCI Express Interface Control Parameters

      285
      • Table 138. PCI Express Interface Control Parameters Usage (Sheet 1 of 2)

        285
    • 3.14.2 PCI Express Interface Status Reporting

      287
      • Table 139. PCI Express Interface Status Reporting Usage

        287
  • 3.15 Root Complex Functionality

    288
  • 3.16 Embedded Bridge Functionality

    288
  • 3.17 Register Definitions

    289
    • Figure 32. ATU Interface Configuration Header Format

      289
    • 3.17.1 Extended Capabilities Registers

      290
      • Figure 33. ATU Interface Extended Configuration Header Format (Power Management)

        290
      • Figure 34. ATU Interface Extended Configuration Header Format (MSI-X Capability)

        290
      • Figure 35. ATU Interface Extended Configuration Header Format (MSI Capability)

        291
      • Figure 36. ATU Interface Extended Configuration Header Format (PCI Express Capability)

        291
      • Figure 37. ATU Interface Extended Configuration Header Format (VPD Capability)

        291
    • 3.17.2 Internal Bus Addresses

      293
      • Table 140. ATU Internal Bus Memory Mapped Register Range Offsets

        293
      • Table 141. ATU PCI Configuration Register Space (Sheet 1 of 3)

        294
    • 3.17.3 ATU Vendor ID Register - ATUVID

      297
      • Table 142. ATU Vendor ID Register - ATUVID

        297
    • 3.17.4 ATU Device ID Register - ATUDID

      297
      • Table 143. ATU Device ID Register - ATUDID

        297
    • 3.17.5 ATU Command Register - ATUCMD

      298
      • Table 144. ATU Command Register - ATUCMD

        298
    • 3.17.6 ATU Status Register - ATUSR

      299
      • Table 145. ATU Status Register - ATUSR

        299
    • 3.17.7 ATU Revision ID Register - ATURID

      300
      • Table 146. ATU Revision ID Register - ATURID

        300
    • 3.17.8 ATU Class Code Register - ATUCCR

      300
      • Table 147. ATU Class Code Register - ATUCCR

        300
    • 3.17.9 ATU Cacheline Size Register - ATUCLSR

      301
      • Table 148. ATU Cacheline Size Register - ATUCLSR

        301
    • 3.17.10 ATU Latency Timer Register - ATULT

      301
      • Table 149. ATU Latency Timer Register - ATULT

        301
    • 3.17.11 ATU Header Type Register - ATUHTR

      302
      • Table 150. ATU Header Type Register - ATUHTR

        302
    • 3.17.12 ATU BIST Register - ATUBISTR

      303
      • Table 151. ATU BIST Register - ATUBISTR

        303
    • 3.17.13 Inbound ATU Base Address Register 0 - IABAR0

      304
      • Table 152. Inbound ATU Base Address Register 0 - IABAR0

        304
    • 3.17.14 Inbound ATU Upper Base Address Register 0 - IAUBAR0

      305
      • Table 153. Inbound ATU Upper Base Address Register 0 - IAUBAR0

        305
    • 3.17.15 Determining Block Sizes for Base Address Registers

      306
      • Table 154. Memory Block Size Read Response

        306
      • Table 155. ATU Base Registers and Associated Limit Registers

        307
    • 3.17.16 Inbound ATU Base Address Register 1 - IABAR1

      308
      • Table 156. Inbound ATU Base Address Register 1 - IABAR1

        308
    • 3.17.17 Inbound ATU Upper Base Address Register 1 - IAUBAR1

      309
      • Table 157. Inbound ATU Upper Base Address Register 1 - IAUBAR1

        309
    • 3.17.18 Inbound ATU Base Address Register 2 - IABAR2

      310
      • Table 158. Inbound ATU Base Address Register 2 - IABAR2

        310
    • 3.17.19 Inbound ATU Upper Base Address Register 2 - IAUBAR2

      311
      • Table 159. Inbound ATU Upper Base Address Register 2 - IAUBAR2

        311
    • 3.17.20 ATU Subsystem Vendor ID Register - ASVIR

      312
      • Table 160. ATU Subsystem Vendor ID Register - ASVIR

        312
    • 3.17.21 ATU Subsystem ID Register - ASIR

      312
      • Table 161. ATU Subsystem ID Register - ASIR

        312
    • 3.17.22 Expansion ROM Base Address Register - ERBAR

      313
      • Table 162. Expansion ROM Base Address Register -ERBAR

        313
    • 3.17.23 ATU Capabilities Pointer Register - ATU_Cap_Ptr

      314
      • Table 163. ATU Capabilities Pointer Register - ATU_Cap_Ptr

        314
    • 3.17.24 ATU Interrupt Line Register - ATUILR

      315
      • Table 164. ATU Interrupt Line Register - ATUILR

        315
    • 3.17.25 ATU Interrupt Pin Register - ATUIPR

      316
      • Table 165. ATU Interrupt Pin Register - ATUIPR

        316
    • 3.17.26 ATU Minimum Grant Register - ATUMGNT

      316
      • Table 166. ATU Minimum Grant Register - ATUMGNT

        316
    • 3.17.27 ATU Maximum Latency Register - ATUMLAT

      317
      • Table 167. ATU Maximum Latency Register - ATUMLAT

        317
    • 3.17.28 Inbound ATU Limit Register 0 - IALR0

      318
      • Table 168. Inbound ATU Limit Register 0 - IALR0

        318
    • 3.17.29 Inbound ATU Translate Value Register 0 - IATVR0

      319
      • Table 169. Inbound ATU Translate Value Register 0 - IATVR0

        319
    • 3.17.30 Inbound ATU Upper Translate Value Register 0 - IAUTVR0

      319
      • Table 170. Inbound ATU Upper Translate Value Register 0 - IAUTVR0

        319
    • 3.17.31 Inbound ATU Limit Register 1 - IALR1

      320
      • Table 171. Inbound ATU Limit Register 1 - IALR1

        320
    • 3.17.32 Inbound ATU Translate Value Register 1 - IATVR1

      321
      • Table 172. Inbound ATU Translate Value Register 1 - IATVR1

        321
    • 3.17.33 Inbound ATU Upper Translate Value Register 1 - IAUTVR1

      321
      • Table 173. Inbound ATU Upper Translate Value Register 1 - IAUTVR1

        321
    • 3.17.34 Inbound ATU Limit Register 2 - IALR2

      322
      • Table 174. Inbound ATU Limit Register 2 - IALR2

        322
    • 3.17.35 Inbound ATU Translate Value Register 2 - IATVR2

      323
      • Table 175. Inbound ATU Translate Value Register 2 - IATVR2

        323
    • 3.17.36 Inbound ATU Upper Translate Value Register 2 - IAUTVR2

      324
      • Table 176. Inbound ATU Upper Translate Value Register 2 - IAUTVR2

        324
    • 3.17.37 Expansion ROM Limit Register - ERLR

      324
      • Table 177. Expansion ROM Limit Register - ERLR

        324
    • 3.17.38 Expansion ROM Translate Value Register - ERTVR

      325
      • Table 178. Expansion ROM Translate Value Register - ERTVR

        325
    • 3.17.39 Expansion ROM Upper Translate Value Register - ERUTVR

      325
      • Table 179. Expansion ROM Upper Translate Value Register - ERUTVR

        325
    • 3.17.40 ATU Configuration Register - ATUCR

      326
      • Table 180. ATU Configuration Register - ATUCR

        326
    • 3.17.41 PCI Configuration and Status Register - PCSR

      327
      • Table 181. PCI Configuration and Status Register - PCSR (Sheet 1 of 2)

        327
    • 3.17.42 ATU Interrupt Status Register - ATUISR

      329
      • Table 182. ATU Interrupt Status Register - ATUISR (Sheet 1 of 3)

        329
    • 3.17.43 ATU Interrupt Mask Register - ATUIMR

      332
      • Table 183. ATU Interrupt Mask Register - ATUIMR

        332
    • 3.17.44 PCI Express Message Control/Status Register - PEMCSR

      333
      • Table 184. PCI Express Message Control and Status Register - PEMCSR

        333
    • 3.17.45 PCI Express Link Control/Status Register - PELCSR

      334
      • Table 185. PCI Express Link Control and Status Register - PELCSR

        334
    • 3.17.46 VPD Capability Identifier Register - VPD_Cap_ID

      335
      • Table 186. VPD Capability Identifier Register - VPD_Cap_ID

        335
    • 3.17.47 VPD Next Item Pointer Register - VPD_Next_Item_Ptr

      335
      • Table 187. VPD Next Item Pointer Register - VPD_Next_Item_Ptr

        335
    • 3.17.48 VPD Address Register - VPDAR

      336
      • Table 188. VPD Address Register - VPDAR

        336
    • 3.17.49 VPD Data Register - VPDDR

      336
      • Table 189. VPD Data Register - VPDDR

        336
    • 3.17.50 PM Capability Identifier Register - PM_Cap_ID

      337
      • Table 190. PM_Capability Identifier Register - PM_Cap_ID

        337
    • 3.17.51 PM Next Item Pointer Register - PM_Next_Item_Ptr

      337
      • Table 191. PM Next Item Pointer Register - PM_Next_Item_Ptr

        337
    • 3.17.52 ATU Power Management Capabilities Register - APMCR

      338
      • Table 192. ATU Power Management Capabilities Register - APMCR

        338
    • 3.17.53 ATU Power Management Control/Status Register - APMCSR

      339
      • Table 193. ATU Power Management Control/Status Register - APMCSR

        339
    • 3.17.54 ATU Scratch Pad Register - ATUSPR

      340
      • Table 194. Scratch Pad Register - ATUSPR

        340
    • 3.17.55 PCI Express Capability List Register - PCIE_CAPID

      340
      • Table 195. PCI Express Capability Identifier Register - PCIE_CAPID

        340
    • 3.17.56 PCI Express Next Item Pointer Register - PCIE_NXTP

      341
      • Table 196. PCI Express Next Item Pointer Register - PCIE_NXTP

        341
    • 3.17.57 PCI Express Capabilities Register - PCIE_CAP

      342
      • Table 197. PCI Express Capabilities Register PCIE_CAP

        342
    • 3.17.58 PCI Express Device Capabilities Register - PCIE_DCAP

      343
      • Table 198. PCI Express Device Capabilities Register - PCIE_DCAP

        343
    • 3.17.59 PCI Express Device Control Register - PE_DCTL

      344
      • Table 199. PCI Express Device Control Register - PE_DCTL (Sheet 1 of 2)

        344
    • 3.17.60 PCI Express Device Status Register - PE_DSTS

      346
      • Table 200. PCI Express Device Status Register PE_DSTS

        346
    • 3.17.61 PCI Express Link Capabilities Register - PE_LCAP

      347
      • Table 201. PCI Express Link Capabilities Register - PE_LCAP

        347
    • 3.17.62 PCI Express Link Control Register - PE_LCTL

      348
      • Table 202. PCI Express Link Control Register PE_LCTL

        348
    • 3.17.63 PCI Express Link Status Register - PE_LSTS

      349
      • Table 203. PCI Express Link Status Register PE_LSTS

        349
    • 3.17.64 PCI Express Slot Capabilities Register - PE_SCAP

      350
      • Table 204. PCI Express Slot Capabilities Register - PE_SCAP

        350
    • 3.17.65 PCI Express Slot Control Register - PE_SCR

      351
      • Table 205. PCI Express Slot Control Register PE_SCR

        351
    • 3.17.66 PCI Express Slot Status Register - PE_SSTS

      352
      • Table 206. PCI Express Slot Status Register PE_SSTS

        352
    • 3.17.67 PCI Express Root Control Register - PE_RCR

      353
      • Table 207. PCI Express Root Control Register - PE_RCR

        353
    • 3.17.68 PCI Express Root Status Register - PE_RSR

      354
      • Table 208. PCI Express Root Status Register PE_RSR

        354
    • 3.17.69 PCI Express Advanced Error Capability Identifier - ADVERR_CAPID

      354
      • Table 209. PCI Express Advanced Error Capability Identifier - ADVERR_CAPID

        354
    • 3.17.70 PCI Express Uncorrectable Error Status - ERRUNC_STS

      355
      • Table 210. PCI Express Uncorrectable Error Status - ERRUNC_STS

        355
    • 3.17.71 PCI Express Uncorrectable Error Mask - ERRUNC_MSK

      356
      • Table 211. PCI Express Uncorrectable Error Mask - ERRUNC_MSK

        356
    • 3.17.72 PCI Express Uncorrectable Error Severity - ERRUNC_SEV

      357
      • Table 212. PCI Express Uncorrectable Error Severity - ERRUNC_SEV

        357
    • 3.17.73 PCI Express Correctable Error Status - ERRCOR_STS

      358
      • Table 213. PCI Express Correctable Error Status - ERRCOR_STS

        358
    • 3.17.74 PCI Express Correctable Error Mask - ERRCOR_MSK

      359
      • Table 214. PCI Express Correctable Error Mask - ERRCOR_MSK

        359
    • 3.17.75 Advanced Error Control and Capability Register - ADVERR_CTL

      360
      • Table 215. Advanced Error Control and Capability Register - ADVERR_CTL

        360
    • 3.17.76 PCI Express Advanced Error Header Log - ADVERR_LOG0

      360
      • Table 216. PCI Express Advanced Error Header Log - ADVERR_LOG0

        360
    • 3.17.77 PCI Express Advanced Error Header Log - ADVERR_LOG1

      361
      • Table 217. PCI Express Advanced Error Header Log - ADVERR_LOG1

        361
    • 3.17.78 PCI Express Advanced Error Header Log - ADVERR_LOG2

      361
      • Table 218. PCI Express Advanced Error Header Log - ADVERR_LOG2

        361
    • 3.17.79 PCI Express Advanced Error Header Log - ADVERR_LOG3

      362
      • Table 219. PCI Express Advanced Error Header Log - ADVERR_LOG3

        362
    • 3.17.80 Root Error Command Register - RERR_CMD

      362
      • Table 220. Root Error Command Register - RERR_CMD

        362
    • 3.17.81 Root Error Status Register

      363
      • Table 221. Root Error Status Register - RERR_SR

        363
    • 3.17.82 Error Source Identification Register - RERR_ID

      364
      • Table 222. Error Source Identification Register RERR_ID

        364
    • 3.17.83 Device Serial Number Capability - DSN_CAP

      364
      • Table 223. Device Serial Number Capability - DSN_CAP

        364
    • 3.17.84 Device Serial Number Lower DW Register - DSN_LDW

      365
      • Table 224. Device Serial Number Lower DW Register - DSN_LDW

        365
    • 3.17.85 Device Serial Number Upper DW Register - DSN_UDW

      365
      • Table 225. Device Serial Number Upper DW Register - DSN_UDW

        365
    • 3.17.86 PCI Express Advisory Error Control Register - PIE_AEC

      366
      • Table 226. PCI Express Advisory Error Control Register PIE_AEC

        366
    • 3.17.87 Power Budgeting Enhanced Capability Header - PWRBGT_CAPID

      367
      • Table 227. Power Budgeting Enhanced Capability Header - PWRBGT_CAPID

        367
    • 3.17.88 Power Budgeting Data Select Register - PWRBGT_DSEL

      367
      • Table 228. Power Budgeting Data Select Register - PWRBGT_DSEL

        367
    • 3.17.89 Power Budgeting Data Register - PWRBGT_DATA

      368
      • Table 229. Power Budgeting Data Register - PWRBGT_DATA

        368
    • 3.17.90 Power Budgeting Capability Register - PWRBGT_CAP

      369
      • Table 230. Power Budgeting Capability Register - PWRBGT_CAP

        369
    • 3.17.91 Power Budgeting Information Registers[0:23]-PWRBGT_INFO[0:23]

      370
      • Table 231. Power Budgeting Information Registers[0:23]-PWRBGT_INFO[0:23]

        370
    • 3.17.92 Outbound I/O Base Address Register - OIOBAR

      371
      • Table 232. Outbound I/O Base Address Register - OIOBAR

        371
    • 3.17.93 Outbound I/O Window Translate Value Register - OIOWTVR

      372
      • Table 233. Outbound I/O Window Translate Value Register - OIOWTVR

        372
    • 3.17.94 Outbound Upper Memory Window Base Address Register 0 - OUMBAR0

      373
      • Table 234. Outbound Upper Memory Window Base Address Register 0 - OUMBAR0

        373
    • 3.17.95 Outbound Upper 32-bit Memory Window Translate Value Register 0 - OUMWTVR0

      374
      • Table 235. Outbound Upper 32-bit Memory Window Translate Value Register 0- OUMWTVR0

        374
    • 3.17.96 Outbound Upper Memory Window Base Address Register 1 - OUMBAR1

      375
      • Table 236. Outbound Upper Memory Window Base Address Register 1 - OUMBAR1

        375
    • 3.17.97 Outbound Upper 32-bit Memory Window Translate Value Register 1 - OUMWTVR1

      376
      • Table 237. Outbound Upper 32-bit Memory Window Translate Value Register 1- OUMWTVR1

        376
    • 3.17.98 Outbound Upper Memory Window Base Address Register 2 - OUMBAR2

      377
      • Table 238. Outbound Upper Memory Window Base Address Register 2- OUMBAR2

        377
    • 3.17.99 Outbound Upper 32-bit Memory Window Translate Value Register 2 - OUMWTVR2

      378
      • Table 239. Outbound Upper 32-bit Memory Window Translate Value Register 2- OUMWTVR2

        378
    • 3.17.100 Outbound Upper Memory Window Base Address Register 3 - OUMBAR3

      379
      • Table 240. Outbound Upper Memory Window Base Address Register 3 - OUMBAR3

        379
    • 3.17.101 Outbound Upper 32-bit Memory Window Translate Value Register 3 - OUMWTVR3

      380
      • Table 241. Outbound Upper 32-bit Memory Window Translate Value Register 3- OUMWTVR3

        380
    • 3.17.102 Outbound Configuration Cycle Address Register - OCCAR

      381
      • Table 242. Outbound Configuration Cycle Address Register - OCCAR

        381
    • 3.17.103 Outbound Configuration Cycle Data Register - OCCDR

      382
      • Table 243. Outbound Configuration Cycle Data Register - OCCDR

        382
    • 3.17.104 Outbound Configuration Cycle Function Number - OCCFN

      383
      • Table 244. Outbound Configuration Cycle Function Number - OCCFN

        383
    • 3.17.105 Inbound Vendor Message Header Register 0 - IVMHR0

      384
      • Table 245. Inbound Vendor Defined Message Header Register0 - IVMHR0

        384
      • Figure 38. PCI Express Vendor_Defined Message Header

        384
    • 3.17.106 Inbound Vendor Message Header Register 1 - IVMHR1

      385
      • Table 246. Inbound Vendor Defined Message Header Register 1 - IVMHR1

        385
    • 3.17.107 Inbound Vendor Message Header Register 2 - IVMHR2

      386
      • Table 247. Inbound Vendor Defined Message Header Register 2 - IVMHR2

        386
    • 3.17.108 Inbound Vendor Message Header Register 3 - IVMHR3

      387
      • Table 248. Inbound Vendor Defined Message Header Register 3 - IVMHR3

        387
    • 3.17.109 Inbound Vendor Message Payload Register - IVMPR

      387
      • Table 249. Inbound Vendor Defined Message Payload Register - IVMPR

        387
    • 3.17.110 Outbound Vendor Message Header Register 0 - OVMHR0

      388
      • Table 250. Outbound Vendor Defined Message Header Register0 - OVMHR0

        388
    • 3.17.111 Outbound Vendor Message Header Register 1 - OVMHR1

      389
      • Table 251. Outbound Vendor Defined Message Header Register 1 - OVMHR1

        389
    • 3.17.112 Outbound Vendor Message Header Register 2 - OVMHR2

      390
      • Table 252. Outbound Vendor Defined Message Header Register 2 - OVMHR2

        390
    • 3.17.113 Outbound Vendor Message Header Register 3 - OVMHR3

      390
      • Table 253. Outbound Vendor Defined Message Header Register 3 - OVMHR3

        390
    • 3.17.114 Outbound Vendor Message Payload Register - OVMPR

      391
      • Table 254. Outbound Vendor Defined Message Payload Register - OVMPR

        391
    • 3.17.115 PCI Interface Error Control and Status Register - PIE_CSR

      392
      • Table 255. PCI Interface Error Control and Status Register - PIE_CSR

        392
    • 3.17.116 PCI Interface Error Status - PIE_STS

      393
      • Table 256. PCI Interface Error Status - PIE_STS

        393
    • 3.17.117 PCI Interface Error Mask - PIE_MSK

      394
      • Table 257. PCI Interface Error Mask - PIE_MSK

        394
    • 3.17.118 PCI Interface Error Header Log - PIE_LOG0

      395
      • Table 258. PCI Interface Error Header Log - PIE_LOG0

        395
    • 3.17.119 PCI Interface Error Header Log 1 - PIE_LOG1

      395
      • Table 259. PCI Interface Error Header Log 1 - PIE_LOG1

        395
    • 3.17.120 PCI Interface Error Header Log 2 - PIE_LOG2

      396
      • Table 260. PCI Interface Error Header Log 2 - PIE_LOG2

        396
    • 3.17.121 PCI Interface Error Header Log - PIE_LOG3

      396
      • Table 261. PCI Interface Error Header Log - PIE_LOG3

        396
    • 3.17.122 PCI Interface Error Descriptor Log

      397
      • Table 262. PCI Interface Error Descriptor Log - PIE_DLOG

        397
    • 3.17.123 ATU Reset Control Register - ATURCR

      397
      • Table 263. ATU Reset Control Register - ATURCR

        397
• 4.0 Messaging Unit

  398
  • 4.1 Overview

    398
  • 4.2 Theory of Operation

    399
    • Figure 39. PCI Memory Map

      400
    • Figure 40. Internal Bus Memory Map

      401
    • Table 264. MU Summary

      401
    • 4.2.1 Transaction Ordering

      402
  • 4.3 Message Registers

    403
    • 4.3.1 Outbound Messages

      403
    • 4.3.2 Inbound Messages

      403
  • 4.4 Doorbell Registers

    404
    • 4.4.1 Outbound Doorbells

      404
    • 4.4.2 Inbound Doorbells

      404
  • 4.5 Messaging Unit Error Conditions

    405
  • 4.6 Message-Signaled Interrupts

    406
    • 4.6.1 MSI Capability Structure

      406
    • 4.6.2 MSI-X Capability and Table Structures

      407
      • Figure 41. MSI-X Table and PBA Address Mapping Layout relative to the Host Interface

        408
      • Figure 42. MSI-X Table and PBA Address Mapping Layout relative to the Internal Bus

        409
    • 4.6.3 Level-Triggered Versus Edge-Triggered Interrupts

      409
  • 4.7 Register Definitions

    410
    • Table 265. Message Unit Registers

      411
    • 4.7.1 Inbound Message Register - IMRx

      412
      • Table 266. Inbound Message Register - IMRx

        412
    • 4.7.2 Outbound Message Register - OMRx

      412
      • Table 267. Outbound Message Register - OMRx

        412
    • 4.7.3 Inbound Doorbell Register - IDR

      413
      • Table 268. Inbound Doorbell Register - IDR

        413
    • 4.7.4 Inbound Interrupt Status Register - IISR

      414
      • Table 269. Inbound Interrupt Status Register - IISR

        414
    • 4.7.5 Inbound Interrupt Mask Register - IIMR

      415
      • Table 270. Inbound Interrupt Mask Register - IIMR

        415
    • 4.7.6 Outbound Doorbell Register - ODR

      416
      • Table 271. Outbound Doorbell Register - ODR

        416
    • 4.7.7 Outbound Interrupt Status Register - OISR

      417
      • Table 272. Outbound Interrupt Status Register - OISR

        417
    • 4.7.8 Outbound Interrupt Mask Register - OIMR

      418
      • Table 273. Outbound Interrupt Mask Register - OIMR

        418
    • 4.7.9 Inbound Reset Control and Status Register - IRCSR

      419
      • Table 274. Inbound Reset Control and Status Register - IRCSR

        419
    • 4.7.10 Outbound Reset Control and Status Register - ORCSR

      420
      • Table 275. Outbound Reset Control and Status Register - ORCSR

        420
    • 4.7.11 MSI Inbound Message Register - MIMR

      421
      • Table 276. MSI Inbound Message Register - MIMR

        421
    • 4.7.12 MU Configuration Register - MUCR

      422
      • Table 277. MU Configuration Register - MUCR

        422
    • 4.7.13 MU Base Address Register - MUBAR

      423
      • Table 278. MU Base Address Register - MUBAR

        423
    • 4.7.14 MU Upper Base Address Register - MUUBAR

      424
      • Table 279. MU Upper Base Address Register - MUUBAR

        424
    • 4.7.15 MU MSI-X Table Message Address Registers - M_MT_MAR[0:7]

      425
      • Table 280. MU MSI-X Table Message Address Registers - M_MT_MAR [0:7]

        425
    • 4.7.16 MU MSI-X Table Message Upper Address Registers - M_MT_MUAR[0:7]

      426
      • Table 281. MU MSI-X Table Message Upper Address Registers - M_MT_MUAR [0:7]

        426
    • 4.7.17 MU MSI-X Table Message Data Registers - M_MT_MDR[0:7]

      427
      • Table 282. MU MSI-X Table Message Upper Address Registers - M_MT_MUAR [0:7]

        427
    • 4.7.18 MU MSI-X Table Message Vector Control Registers - M_MT_MVCR[0:7]

      428
      • Table 283. MU MSI-X Table Message Vector Control Registers - M_MT_MVCR [0:7]

        428
    • 4.7.19 MU MSI-X Pending Bits Array Register - M_MPBAR

      429
      • Table 284. MU MSI-X Pending Bits Array Register - M_MPBAR

        429
    • 4.7.20 MSI Capability Identifier Register - Cap_ID

      429
      • Table 285. MSI Capability Identifier Register - MSI_Cap_ID

        429
    • 4.7.21 MSI Next Item Pointer Register - MSI_Next_Ptr

      430
      • Table 286. MSI Next Item Pointer Register - MSI_Next_Ptr

        430
    • 4.7.22 Message Control Register - Message_Control

      431
      • Table 287. Message Control Register - Message_Control

        431
    • 4.7.23 Message Address Register - Message_Address

      432
      • Table 288. Message Address Register - Message_Address

        432
    • 4.7.24 Message Upper Address Register - Message_Upper_Address

      433
      • Table 289. Message Upper Address Register - Message_Upper_Address

        433
    • 4.7.25 Message Data Register- Message_Data

      434
      • Table 290. Message Data Register - Message_Data

        434
    • 4.7.26 MSI-X Capability Identifier Register - MSI-X_Cap_ID

      435
      • Table 291. MSI-X_Capability Identifier Register - MSI-X_Cap_ID

        435
    • 4.7.27 MSI-X Next Item Pointer Register - MSI-X_Next_Item_Ptr

      436
      • Table 292. MSI-X Next Item Pointer Register - MSI-X_Next_Item_Ptr

        436
    • 4.7.28 MSI-X Message Control Register - MSI-X_MCR

      437
      • Table 293. MSI-X Message Control Register - MSI-X_MCR

        437
    • 4.7.29 MSI-X Table Offset Register - MSI-X_Table_Offset

      438
      • Table 294. MSI-X Table Offset Register - MSI-X_Table_Offset

        438
    • 4.7.30 MSI-X Pending Bit Array Offset Register - MSI-X_PBA_Offset

      439
      • Table 295. MSI-X Pending Bit Array Offset Register - MSI-X_PBA Offset

        439
    • 4.7.31 MU MSI-X Control Register X - MMCRx

      440
      • Table 296. MU MSI-X Control Register X - MMCRx

        440
    • 4.7.32 Inbound MSI Interrupt Pending Register x - IMIPRx

      441
      • Table 297. Inbound MSI Interrupt Pending Registers - IMIPR [0:3]

        441
  • 4.8 Power/Default Status

    441
• 5.0 SRAM DMA Unit (SDMA)

  442
  • 5.1 Introduction

    442
  • 5.2 Overview

    442
  • 5.3 Theory of Operation

    443
    • 5.3.1 Interrupt Control for SDMA

      445
  • 5.4 Register Definitions

    446
    • Table 298. SDMA Controller Unit Registers

      446
    • 5.4.1 LocalToHost Destination Lower Address Register - L2H_DLAR

      447
      • Table 299. LocalToHost Destination Lower Address Register - L2H_DLAR

        447
    • 5.4.2 LocalToHost Destination Upper Address Register - L2H_DUAR

      447
      • Table 300. LocalToHost Destination Upper Address Register - L2H_DUAR

        447
    • 5.4.3 LocalToHost Source Lower Address Register - L2H_SLAR

      448
      • Table 301. LocalToHost Source Lower Address Register - L2H_SLAR

        448
    • 5.4.4 LocalToHost Byte Count Register - L2H_BCR

      449
      • Table 302. LocalToHost Byte Count Register - L2H_BCR

        449
    • 5.4.5 LocalToHost Interrupt Counter/Acknowledge Register L2H_ICAR

      450
      • Table 303. LocalToHost Interrupt Counter/Acknowledge Register - L2H_ICAR

        450
    • 5.4.6 LocalToHost Control/Status Register - L2H_CSR

      451
      • Table 304. LocalToHost Control/Status Register - L2H_CSR

        451
    • 5.4.7 LocalToHost Byte Swap Control Register - L2H_BSCR

      452
      • Table 305. LocalToHost Byte Swap Control Register - L2H_BSCR

        452
    • 5.4.8 HostToLocal Destination Lower Address Register - H2L_DLAR

      452
      • Table 306. HostToLocal Destination Lower Address Register - H2L_DLAR

        452
    • 5.4.9 HostToLocal Source Upper Address Register - H2L_SUAR

      453
      • Table 307. HostToLocal Source Upper Address Register - H2L_SUAR

        453
    • 5.4.10 HostToLocal Source Lower Address Register - H2L_SLAR

      453
      • Table 308. HostToLocal Source Lower Address Register - H2L_SLAR

        453
    • 5.4.11 HostToLocal Byte Count Register - H2L_BCR

      454
      • Table 309. HostToLocal Byte Count Register - H2L_BCR

        454
    • 5.4.12 HostToLocal Interrupt Counter/Acknowledge Register - H2L_ICAR

      455
      • Table 310. HostToLocal Interrupt Counter/Acknowledge Register - H2L_ICAR

        455
    • 5.4.13 HostToLocal Control/Status Register - H2L_CSR

      456
      • Table 311. HostToLocal Control/Status Register - H2L_CSR

        456
    • 5.4.14 HostToLocal Byte Swap Control Register - H2L_BSCR

      457
      • Table 312. HostToLocal Byte Swap Control Register - H2L_BSCR

        457
• 6.0 SGPIO Unit

  458
  • 6.1 Overview

    458
    • Figure 43. SGPIO Bus Overview

      459
  • 6.2 Theory of Operation

    460
    • Figure 44. SGPIO Repeating Bit Stream

      460
    • 6.2.1 SGPIO SClock Output Signal

      460
    • 6.2.2 SGPIO SLoad Output Signal

      460
      • Figure 45. SLoad Signal

        460
    • 6.2.3 SDataOut

      461
      • Figure 46. SDataOut Signal

        461
    • 6.2.4 SGPIO SDataIn Signal

      461
      • Figure 47. SDataIn Signal

        461
  • 6.3 Clock Requirements

    462
    • Figure 48. Clock Structure

      462
  • 6.4 Output Signals

    463
    • Figure 49. SGPIO Output OD0 Signal

      463
    • Figure 50. SGPIO Output OD1 Signal

      464
    • Figure 51. SGPIO Output OD2 Signal

      464
    • 6.4.1 Protocol Engine Input Signals

      465
      • Table 313. SGPIO Input Mapping (Sheet 1 of 2)

        465
      • 6.4.1.1 JOG Requirements

        467
      • 6.4.1.2 Protocol Engine Pre-Conditioning Requirements

        467
    • 6.4.2 Programmable Blink Patterns

      468
  • 6.5 SGPIO Unit Mode of Operations

    469
    • Figure 52. Output Signal Routing

      469
    • Table 314. Example 1: Multiplexer Block Outputs for SGPIO Unit 0 in Direct LED Mode

      470
    • Table 315. Example 2: Multiplexer Block Outputs for SGPIO Unit 1 in SGPIO Mode

      470
    • Table 316. SGPIO Unit 0 Multiplexer Block Outputs for Example 2

      471
    • Table 317. SGPIO Unit 1 Multiplexer Block Outputs for Example 2

      471
    • 6.5.1 Pin Multiplexing

      472
      • Table 318. SGPIO Unit 0 Pin Multiplexing

        472
      • Figure 53. Intel® 413808 and 413812 I/O Controllers in TPER Mode SGPIO Unit 0 Pin Mapping

        472
      • Table 319. SGPIO Unit 1 Pin Multiplexing

        473
      • Figure 54. 4138xx SGPIO Unit 1 Pin Mapping

        473
  • 6.6 Register Definitions

    474
    • Table 320. SGPIO Memory-Mapped Rejecters

      474
    • 6.6.1 SGPIO Interface Control Register x - SGICRx

      475
      • Table 321. SGPIO Interface Control Register x - SGICRx

        475
    • 6.6.2 SGPIO Programmable Blink Register x - SGPBRx

      476
      • Table 322. SGPIO Programmable Blink Register x - SGPBRx (Sheet 1 of 2)

        476
    • 6.6.3 SGPIO Start Drive Lower Register x - SGSDLRx

      478
      • Table 323. SGPIO Start Drive Lower Register x - SGSDLRx (Sheet 1 of 2)

        478
    • 6.6.4 SGPIO Start Drive Upper Register x - SGSDURx

      480
      • Table 324. SGPIO Start Drive Upper Register x - SGSDURx (Sheet 1 of 2)

        480
    • 6.6.5 SGPIO Serial Input Data Lower Register x - SGSIDLRx

      482
      • Table 325. SGPIO Serial Input Data Lower Register x - SGSIDLRx

        482
    • 6.6.6 SGPIO Serial Input Data Upper Register x - SGSIDURx

      483
      • Table 326. SGPIO Serial Input Data Upper Register x - SGSIDURx

        483
    • 6.6.7 SGPIO Vendor Specific Code Register x - SGVSCRx

      483
      • Table 327. SGPIO Vendor Specific Code Register x - SGVSCRx

        483
    • 6.6.8 SGPIO Output Data Select Register[0:7] x - SGODSR[0:7]x

      484
      • Table 328. SGPIO Output Data Select Register[0:7] x - SGODSR[0:7]x

        484
• 7.0 System Controller (SC) and Internal Bus Bridge

  485
  • 7.1 Overview

    485
  • 7.2 Theory of Operation

    486
    • 7.2.1 System Controller

      486
    • 7.2.2 Internal Bus Requester IDs

      487
      • Table 329. Intel® 413808 and 413812 I/O Controllers in TPER Mode Initiator IDs

        487
    • 7.2.3 Parity Testing

      488
      • Figure 55. Typical Internal Bus System Controller Block Diagram

        488
      • Table 330. Address and Data Parity Testing Initiator IDs

        489
      • Table 331. Data Parity Testing Completer IDs

        489
  • 7.3 Internal Bus Bridge

    490
    • 7.3.1 Theory of Operation

      490
    • 7.3.2 Internal Bus Commands

      491
      • Table 332. Bridge supported Internal Bus Commands

        491
    • 7.3.3 Transaction Queues

      491
    • 7.3.4 Bridge Memory Window

      492
    • 7.3.5 Ordering and Passing Rules

      493
      • Table 333. Ordering and Passing Rules for both Inbound and Outbound Transactions

        493
      • 7.3.5.1 Strong Ordering Rule Requirements

        493
    • 7.3.6 Parity Support

      494
      • 7.3.6.1 Address Parity Generation

        494
      • 7.3.6.2 Address Parity Checking

        494
      • 7.3.6.3 Data Parity on Outbound Transactions

        494
      • 7.3.6.4 Data Parity on Inbound Transactions

        494
    • 7.3.7 Error Detection and Handling

      495
      • 7.3.7.1 Bridge North Internal Bus Interface Error

        495
      • 7.3.7.2 Bridge South Internal Bus Interface Error

        496
  • 7.4 System Controller Register Definitions

    497
  • 7.5 Internal Bus Bridge Register Definitions

    498
    • 7.5.1 Internal Bus Arbitration Control Register - IBACR

      499
      • Table 334. Internal Bus Arbitration Control Register - IBACR (Sheet 1 of 2)

        499
    • 7.5.2 South Internal Bus Address Test Control Register - SIBATCR

      501
      • Table 335. South Internal Bus Address Test Control Register - SIBATCR

        501
    • 7.5.3 South Internal Bus Data Test Control Register - SIBDTCR

      502
      • Table 336. South Internal Bus Data Test Control Register - SIBDTCR

        502
    • 7.5.4 Peripheral Memory-Mapped Register Base Address Register - PMMRBAR

      503
      • Table 337. Peripheral Memory-Mapped Register Base Address Register - PMMRBAR

        503
    • 7.5.5 Determining Block Sizes for Memory Windows

      504
      • Table 338. Memory Block Size Limit Register Value

        504
    • 7.5.6 Bridge Window Base Address Register - BWBAR

      505
      • Table 339. Bridge Window Base Address Register - BWBAR

        505
    • 7.5.7 Bridge Window Upper Base Address Register - BWUBAR

      506
      • Table 340. Bridge Window Upper Base Address Register - BWUBAR

        506
    • 7.5.8 Bridge Window Limit Register - BWLR

      507
      • Table 341. Bridge Limit Register - BWLR

        507
    • 7.5.9 Bridge Error Control and Status Register - BECSR

      508
      • Table 342. Bridge Error Control and Status Register - BECSR (Sheet 1 of 2)

        508
    • 7.5.10 Bridge Error Address Register - BERAR

      510
      • Table 343. Bridge Error Address Register - BERAR

        510
    • 7.5.11 Bridge Error Upper Address Register - BERUAR

      510
      • Table 344. Bridge Error Upper Address Register - BERUAR

        510
• 8.0 SRAM Memory Controller

  511
  • 8.1 Overview

    511
  • 8.2 Glossary

    512
    • Table 345. Commonly Used Terms

      512
  • 8.3 Theory of Operation

    513
    • 8.3.1 Functional Block

      513
      • Figure 56. Intel® 413808 and 413812 I/O Controllers in TPER Mode SRAM Memory Controller Block Diagram

        513
      • 8.3.1.1 North Internal Bus Ports

        513
      • 8.3.1.2 Address Decode Blocks

        514
        • 8.3.1.2.1 SRAM Memory Array Space

          514
        • 8.3.1.2.2 Memory-Mapped Register Space

          514
        • 8.3.1.2.3 North Internal Bus Port Address Decode

          514
      • 8.3.1.3 Memory Transaction Queues

        514
        • 8.3.1.3.1 North Internal Bus Port Transaction Queue (NIBPTQ)

          514
      • 8.3.1.4 Configuration Registers

        514
      • 8.3.1.5 SRAM Control Block

        514
        • 8.3.1.5.1 SRAM State Machine and Pipeline Queues

          514
        • 8.3.1.5.2 Error Correction Logic

          515
      • 8.3.1.6 North Internal Bus Port Transaction Ordering

        516
      • 8.3.1.7 SMCU Port Coherency

        516
    • 8.3.2 SRAM Memory Interface Support

      517
      • 8.3.2.1 SRAM Initialization

        517
      • 8.3.2.2 SRAM Read Sequence

        517
      • 8.3.2.3 SRAM Write Sequence

        518
    • 8.3.3 Error Correction and Detection

      519
      • 8.3.3.1 ECC Generation

        520
        • Figure 57. ECC Write Flow

          520
      • 8.3.3.2 ECC Generation for Partial Writes

        521
        • Figure 58. Intel® 413808 and 413812 I/O Controllers G-Matrix (generates the ECC)

          521
      • 8.3.3.3 ECC Checking

        522
        • Table 346. Syndrome Decoding

          522
        • Figure 59. ECC Read Data Flow

          523
        • Figure 60. 4138xx H-Matrix (indicates the single-bit error location)

          524
      • 8.3.3.4 Scrubbing

        526
        • 8.3.3.4.1 ECC Example Using the H-Matrix

          526
      • 8.3.3.5 ECC Disabled

        527
      • 8.3.3.6 ECC Testing

        527
    • 8.3.4 Byte Parity Checking and Generation

      528
      • Figure 61. Logical Data Access Paths with Parity Protection

        528
      • 8.3.4.1 Parity Generation

        529
        • Equation 15. D_PARITY0 = D[0] XOR D[1] XOR D[2] XOR D[3] XOR D[4] XOR D[5] XOR D[6] XOR D[7] XOR BE[0]

          529
        • Table 347. Data Parity Checking/Generation

          529
      • 8.3.4.2 Parity Checking

        530
        • Equation 16. DATA_PARITY_RESULT = D_PARITY0 XOR D[0] XOR D[1] XOR D[2] XOR D[3] XOR D[4] XOR D[5] XOR D[6] XOR D[7] XOR BE[0]

          530
      • 8.3.4.3 Parity Disabled

        530
      • 8.3.4.4 Parity Testing

        530
  • 8.4 ECC Interrupts/Error Conditions

    531
    • Table 348. SMCU Error Response

      531
    • 8.4.1 Single-Bit Error Detection

      532
    • 8.4.2 Multi-bit Error Detection

      533
  • 8.5 Parity Interrupts/Error Conditions

    534
  • 8.6 Register Definitions

    535
    • Table 349. Memory Controller Register

      535
    • 8.6.1 SRAM Base Address Register - SRAMBAR

      536
      • Table 350. SRAM Base Address Register - SRAMBAR

        536
    • 8.6.2 SRAM Upper Base Address Register - SRAMUBAR

      536
      • Table 351. SRAM Upper Base Address Register - SRAMUBAR

        536
    • 8.6.3 SRAM ECC Control Register - SECR

      536
      • Table 352. SRAM ECC Control Register - SECR

        537
    • 8.6.4 SRAM ECC Log Register - SELOGR

      538
      • Table 353. SRAM ECC Log Register - SELOG (Sheet 1 of 2)

        538
    • 8.6.5 SRAM ECC Address Register - SEAR

      540
      • Table 354. SRAM ECC Address Register - SEAR

        540
    • 8.6.6 SRAM ECC Context Address Register - SECAR

      540
      • Table 355. SRAM ECC Context Address Register - SECAR

        540
    • 8.6.7 SRAM ECC Test Register - SECTST

      541
      • Table 356. SRAM ECC Test Register - SECTST

        541
    • 8.6.8 SRAM Parity Control and Status Register - SPARCSR

      542
      • Table 357. SRAM Parity Control and Status Register - SPARCSR

        542
    • 8.6.9 SRAM Parity Address Register - SPAR

      543
      • Table 358. SRAM Parity Address Registers - SPAR

        543
    • 8.6.10 SRAM Parity Upper Address Register - SPUAR

      543
      • Table 359. SRAM Parity Upper Address Register - SPUAR

        543
    • 8.6.11 SRAM Memory Controller Interrupt Status Register - SMCISR

      544
      • Table 360. SRAM Memory Controller Interrupt Status Register - SMCISR

        544
• 9.0 Peripheral Bus Interface Unit

  545
  • Figure 62. The Peripheral Bus Interface Unit

    545
  • 9.1 Overview

    546
  • 9.2 Peripheral Bus Signals

    547
    • 9.2.1 Address Signal Definitions

      547
    • 9.2.2 Data Signal Definitions

      547
    • 9.2.3 Control/Status Signal Definitions

      547
    • 9.2.4 Bus Width

      548
      • Figure 63. Data Width and Low Order Address Lines

        548
    • 9.2.5 Detailed Signal Descriptions

      549
      • Table 361. Bus Signal Descriptions

        549
    • 9.2.6 Flash Memory Support

      550
      • Figure 64. Sixty-Four Mbyte Flash Memory System

        550
      • 9.2.6.1 Flash Read Cycle

        551
        • Figure 65. 120 ns Flash Single Transfer Read Cycle

          551
        • Figure 66. 120 ns Flash Burst Read Cycle

          552
        • Table 362. Flash Wait State Profile Programming1

          552
      • 9.2.6.2 Flash Write Cycle

        553
        • Figure 67. 120 ns Flash Single Write Cycle1

          553
  • 9.3 Register Definitions

    554
    • Table 363. Peripheral Bus Interface Registers

      554
    • 9.3.1 PBI Control Register - PBCR

      555
      • Table 364. PBI Control Register - PBCR

        555
    • 9.3.2 PBI Status Register - PBISR

      555
      • Table 365. PBI Status Register - PBISR

        555
    • 9.3.3 Determining Block Sizes for Memory Windows

      556
      • Table 366. Memory Block Size Limit Register Values

        556
    • 9.3.4 PBI Base Address Register 0 - PBBAR0

      557
      • Table 367. PBI Base Address Register 0 - PBBAR0

        557
    • 9.3.5 PBI Limit Register 0 - PBLR0

      558
      • Table 368. PBI Limit Register 0 - PBLR0

        558
    • 9.3.6 PBI Base Address Register 1 - PBBAR1

      559
      • Table 369. PBI Base Address Register 1 - PBBAR1

        559
    • 9.3.7 PBI Limit Register 1 - PBLR1

      560
      • Table 370. PBI Limit Register 1 - PBLR1

        560
    • 9.3.8 PBI Drive Strength Control Register - PBDSCR

      561
      • Table 371. PBI Drive Strength Control Register - PBDSCR

        561
    • 9.3.9 Processor Frequency Register - PFR

      562
      • Table 372. Processor Frequency Register - PFR

        562
    • 9.3.10 External Strap Status Register 0 - ESSTSR0

      563
      • Table 373. External Strap Status Register 0 - ESSTS0

        563
    • 9.3.11 Unique ID Register 0 - UID0

      564
      • Table 374. Unique ID Register 0 - UID0

        564
    • 9.3.12 Unique ID Register 1 - UID1

      564
      • Table 375. Unique ID Register 1 - UID1

        564
• 10.0 Interrupt Controller Unit

  565
  • 10.1 Overview

    565
  • 10.2 Theory of Operation

    566
    • 10.2.1 Interrupt Controller Unit

      566
  • 10.3 The Intel XScale® Processor Exceptions Architecture

    567
    • 10.3.1 CPSR and SPSR

      567
    • 10.3.2 The Exception Process

      567
    • 10.3.3 Exception Priorities and Vectors

      568
      • Table 376. Exception Priorities And Vectors

        568
    • 10.3.4 Software Requirements For Exception Handling

      568
      • 10.3.4.1 Nesting FIQ and IRQ Exceptions

        568
  • 10.4 Intel® 413808 and 413812 I/O Controllers in TPER Mode External Interrupt Interface

    569
    • 10.4.1 Interrupt Inputs

      569
      • Table 377. Interrupt Input Pin Descriptions

        570
    • 10.4.2 Outbound Interrupts

      571
      • Table 378. Interrupt Output Pin Descriptions

        571
  • 10.5 The Intel® 413808 and 413812 I/O Controllers in TPER Mode Interrupt Controller Unit

    572
    • 10.5.1 Programmer Model

      573
      • 10.5.1.1 Active Interrupt Source Control and Status

        573
        • Figure 68. Interrupt Controller Block Diagram (Active Interrupt Source Registers)

          573
      • 10.5.1.2 Prioritization and Vector Generation for Active Interrupt Sources

        573
        • Figure 69. Interrupt Controller Block Diagram (FIQ/IRQ Interrupt Vector Generation)

          574
    • 10.5.2 Operational Blocks

      575
      • Figure 70. Intel® 413808 and 413812 I/O Controllers in TPER Mode Interrupt Controller Connections

        575
    • 10.5.3 Intel® 413808 and 413812 I/O Controllers in TPER Mode: Internal Peripheral Interrupt

      576
      • 10.5.3.1 Normal Interrupt Sources

        577
        • Table 379. Normal Interrupt Sources

          577
      • 10.5.3.2 Error Interrupt Sources

        578
        • Table 380. Error Interrupt Sources

          578
    • 10.5.4 High-Priority Interrupt (HPI#)

      579
    • 10.5.5 Timer Interrupts

      579
    • 10.5.6 Inter-Processor Interrupts

      579
    • 10.5.7 Intel XScale® Processor Interrupts

      579
    • 10.5.8 Software Interrupts

      579
  • 10.6 Default Status

    580
    • Table 381. Default Interrupt Routing and Status Values

      580
  • 10.7 Interrupt Control Unit Registers

    581
    • Table 382. Interrupt Controller Co-Processor Register Addresses (Sheet 1 of 2)

      581
    • 10.7.1 Interrupt Base Register - INTBASE

      583
      • Table 383. Interrupt Base Register - INTBASE

        583
    • 10.7.2 Interrupt Size Register - INTSIZE

      584
      • Table 384. Interrupt Size Register - INTSIZE

        584
    • 10.7.3 IRQ Interrupt Vector Register - IINTVEC

      585
      • Table 385. IRQ Interrupt Vector Register- IINTVEC

        585
    • 10.7.4 FIQ Interrupt Vector Register - FINTVEC

      586
      • Table 386. FIQ Interrupt Vector Register- FINTVEC

        586
    • 10.7.5 Interrupt Pending Register 0 - INTPND0

      587
      • Table 387. Interrupt Pending Register 0 - INTPND0

        587
    • 10.7.6 Interrupt Pending Register 1 - INTPND1

      588
      • Table 388. Interrupt Pending Register 1 - INTPND1

        588
    • 10.7.7 Interrupt Pending Register 2 - INTPND2

      589
      • Table 389. Interrupt Pending Register 2 - INTPND2

        589
    • 10.7.8 Interrupt Pending Register 3 - INTPND3

      590
      • Table 390. Interrupt Pending Register 3 - INTPND3

        590
    • 10.7.9 Interrupt Control Register 0 - INTCTL0

      591
      • Table 391. Interrupt Control Register 0 - INTCTL0 (Sheet 1 of 2)

        591
    • 10.7.10 Interrupt Control Register 1 - INTCTL1

      593
      • Table 392. Interrupt Control Register 1 - INTCTL1 (Sheet 1 of 2)

        593
    • 10.7.11 Interrupt Control Register 2 - INTCTL2

      595
      • Table 393. Interrupt Control Register 2 - INTCTL2

        595
    • 10.7.12 Interrupt Control Register 3 - INTCTL3

      596
      • Table 394. Interrupt Control Register 3 - INTCTL3 (Sheet 1 of 2)

        596
    • 10.7.13 Interrupt Steering Register 0 - INTSTR0

      598
      • Table 395. Interrupt Steering Register 0 - INTSTR0 (Sheet 1 of 2)

        598
    • 10.7.14 Interrupt Steering Register 1 - INTSTR1

      600
      • Table 396. Interrupt Steering Register 1 - INTSTR1 (Sheet 1 of 2)

        600
    • 10.7.15 Interrupt Steering Register 2 - INTSTR2

      602
      • Table 397. Interrupt Steering Register 2 - INTSTR2

        602
    • 10.7.16 Interrupt Steering Register 3 - INTSTR3

      603
      • Table 398. Interrupt Steering Register 3 - INTSTR3 (Sheet 1 of 2)

        603
    • 10.7.17 IRQ Interrupt Source Register 0 - IINTSRC0

      605
      • Table 399. IRQ Interrupt Source Register 0 - IINTSRC0 (Sheet 1 of 2)

        605
    • 10.7.18 IRQ Interrupt Source Register 1 - IINTSRC1

      607
      • Table 400. IRQ Interrupt Source Register 1 - IINTSRC1 (Sheet 1 of 2)

        607
    • 10.7.19 IRQ Interrupt Source Register 2 - IINTSRC2

      609
      • Table 401. IRQ Interrupt Source Register 2 - IINTSRC2

        609
    • 10.7.20 IRQ Interrupt Source Register 3 - IINTSRC3

      610
      • Table 402. IRQ Interrupt Source Register 3 - IINTSRC3 (Sheet 1 of 2)

        610
    • 10.7.21 FIQ Interrupt Source Register 0 - FINTSRC0

      612
      • Table 403. FIQ Interrupt Source Register 0 - FINTSRC0 (Sheet 1 of 2)

        612
    • 10.7.22 FIQ Interrupt Source Register 1 - FINTSRC1

      614
      • Table 404. FIQ Interrupt Source Register 1 - FINTSRC1 (Sheet 1 of 2)

        614
    • 10.7.23 FIQ Interrupt Source Register 2 - FINTSRC2

      616
      • Table 405. FIQ Interrupt Source Register 2 - FINTSRC2

        616
    • 10.7.24 FIQ Interrupt Source Register 3 - FINTSRC3

      617
      • Table 406. FIQ Interrupt Source Register 3 - FINTSRC3 (Sheet 1 of 2)

        617
    • 10.7.25 Interrupt Priority Register 0 - IPR0

      619
      • Table 407. Interrupt Priority Register 0 - IPR0

        619
    • 10.7.26 Interrupt Priority Register 1 - IPR1

      620
      • Table 408. Interrupt Priority Register 1 - IPR1

        620
    • 10.7.27 Interrupt Priority Register 2 - IPR2

      621
      • Table 409. Interrupt Priority Register 2 - IPR2

        621
    • 10.7.28 Interrupt Priority Register 3 - IPR3

      622
      • Table 410. Interrupt Priority Register 3 - IPR3

        622
    • 10.7.29 Interrupt Priority Register 4 - IPR4

      623
      • Table 411. Interrupt Priority Register 4 - IPR4

        623
    • 10.7.30 Interrupt Priority Register 5 - IPR5

      624
      • Table 412. Interrupt Priority Register 5 - IPR5

        624
    • 10.7.31 Interrupt Priority Register 6 - IPR6

      625
      • Table 413. Interrupt Priority Register 6 - IPR6

        625
    • 10.7.32 Interrupt Priority Register 7 - IPR7

      626
      • Table 414. Interrupt Priority Register 7 - IPR7

        626
• 11.0 Timers

  627
  • Figure 71. Programmable Timer Functional Diagram

    627
  • Table 415. Timer Performance Ranges

    627
  • 11.1 Timer Operation

    628
    • 11.1.1 Basic Programmable Timer Operation

      628
      • Table 416. Timer Mode Register Control Bit Summary

        628
    • 11.1.2 Watch Dog Timer Operation

      629
    • 11.1.3 Load/Store Access Latency for Timer Registers

      630
      • Table 417. Timer Responses to Register Bit Settings

        630
  • 11.2 Timer Interrupts

    631
  • 11.3 Timer State Diagram

    632
    • Figure 72. Timer Unit State Diagram

      632
  • 11.4 Timer Registers

    633
    • Table 418. Timer Registers

      633
    • 11.4.1 Power Up/Reset Initialization

      633
      • Table 419. Timer Power Up Mode Settings

        633
    • 11.4.2 Timer Mode Registers - TMR0:1

      634
      • Table 420. Timer Mode Register - TMRx

        634
      • 11.4.2.1 Bit 0 - Terminal Count Status Bit (TMRx.tc)

        635
      • 11.4.2.2 Bit 1 - Timer Enable (TMRx.enable)

        635
      • 11.4.2.3 Bit 2 - Timer Auto Reload Enable (TMRx.reload)

        635
      • 11.4.2.4 Bit 3 - Timer Register Privileged Read/Write Control (TMRx.pri)

        636
      • 11.4.2.5 Bits 4, 5 - Timer Input Clock Select (TMRx.csel1:0)

        636
        • Table 421. Timer Input Clock (TCLOCK) Frequency Selection

          636
    • 11.4.3 Timer Count Register - TCR0:1

      637
      • Table 422. Timer Count Register - TCRx

        637
    • 11.4.4 Timer Reload Register - TRR0:1

      637
      • Table 423. Timer Reload Register - TRRx

        637
    • 11.4.5 Timer Interrupt Status Register - TISR

      638
      • Table 424. Timer Interrupt Status Register - TISR

        638
    • 11.4.6 Watch Dog Timer Control Register - WDTCR

      639
      • Table 425. Watch Dog Timer Control Register - WDTCR

        639
    • 11.4.7 Watch Dog Timer Setup Register - WDTSR

      639
      • Table 426. Watch Dog Timer Setup Register - WDTSR

        639
  • 11.5 Uncommon TCRX and TRRX Conditions

    640
    • Table 427. Uncommon TMRx Control Bit Settings

      640
• 12.0 SMBus Interface Unit

  641
  • 12.1 Overview

    641
  • 12.2 SMBus Interface

    641
    • Table 428. SMBus Interface Pins

      641
  • 12.3 System Management Bus Interface

    642
    • 12.3.1 SMBus Controller

      643
      • 12.3.1.1 SMBus Commands

        643
        • Table 429. SMBus Command Encoding

          643
      • 12.3.1.2 Initialization Sequence

        644
    • 12.3.2 SMBus Signaling

      645
      • 12.3.2.1 Overview

        645
      • 12.3.2.2 Waveforms

        645
        • Figure 73. Basic SMBus Transfer Waveform

          645
        • 12.3.2.2.1 Start Phase

          645
          • Figure 74. Start (S) / Repeat Start (Sr) Signaling

            645
        • 12.3.2.2.2 Stop Phase

          646
          • Figure 75. Stop (P) Signaling

            646
        • 12.3.2.2.3 ACK/NACK

          646
          • Figure 76. ACK (A) Signaling

            646
          • Figure 77. NACK (N) Signaling

            646
        • 12.3.2.2.4 Wait States

          646
    • 12.3.3 Architecture

      647
      • Table 430. SMBus Interface Registers for Configuration Space Access

        647
      • Table 431. SMBus Interface Registers for Memory Space Access

        647
      • 12.3.3.1 Data Transfer Examples

        649
      • 12.3.3.2 Configuration and Memory Reads

        649
        • Table 432. SMBus Status Byte Encoding

          649
        • Figure 78. DWORD Configuration Read Protocol (SMBus Block Write/Block Read, PEC Enabled)

          649
        • Figure 79. DWORD Memory Read Protocol (SMBus Block Write/Block Read, PEC Enabled)

          650
        • Figure 80. DWORD Configuration Read Protocol (SMBus Word Write/Word Read, PEC Enabled)

          650
        • Figure 81. DWORD Configuration Read Protocol (SMBus Block Write/Block Read, PEC Disabled)

          650
        • Figure 82. DWORD Memory Read Protocol (SMBus Block Write/Block Read, PEC Disabled)

          650
        • Figure 83. DWORD Configuration Read Protocol (SMBus Word Write/Word Read, PEC Disabled)

          651
        • Figure 84. DWORD Memory Read Protocol (SMBus Word Write/(Word, Byte) Read, PEC Enabled)

          651
        • Figure 85. DWORD Memory Read Protocol (SMBus Word Write/Byte Read, PEC Enabled)

          651
      • 12.3.3.3 Configuration and Memory Writes

        652
        • Figure 86. DWORD Configuration Write Protocol (SMBus Block Write, PEC Enabled)

          652
        • Figure 87. DWORD Memory Write Protocol (SMBus Word Write, PEC Enabled)

          652
        • Figure 88. DWORD Configuration Write Protocol (SMBus Byte Write, PEC Enabled)

          653
    • 12.3.4 Error Handling

      654
    • 12.3.5 SMBus Interface Reset

      654
  • 12.4 Register Definitions

    655
    • Table 433. SMBus Register Summary

      655
    • 12.4.1 SMBus Controller Command Register - SM_CMD

      655
      • Table 434. SMBus Controller Command Register - SM_CMD

        655
    • 12.4.2 SMBus Controller Byte Count Register - SM_BC

      656
      • Table 435. SMBus Controller Byte Count Register - SM_BC

        656
    • 12.4.3 SMBus Controller ADDR3 Register - SM_ADDR3

      656
      • Table 436. SMBus Controller ADDR3 Register - SM_ADDR3

        656
    • 12.4.4 SMBus Controller ADDR2 Register - SM_ADDR2

      656
      • Table 437. SMBus Controller ADDR2 Register - SM_ADDR2

        656
    • 12.4.5 SMBus Controller ADDR1 Register Number - SM_ADDR1

      657
      • Table 438. SMBus Controller ADDR1 Register Number - SM_ADDR1

        657
    • 12.4.6 SMBus Controller ADDR0 Register Number - SM_ADDR0

      657
      • Table 439. SMBus Controller ADDR0 Register Number - SM_ADDR0

        657
    • 12.4.7 SMBus Controller Data Register - SM_DATA

      658
      • Table 440. SMBus Controller Data Register - SM_DATA

        658
    • 12.4.8 SMBus Controller Status Register - SM_STS

      658
      • Table 441. SMBus Controller Status Register - SM_STS

        658
• 13.0 UARTs

  659
  • 13.1 Overview

    659
    • 13.1.1 Compatibility with 16550 and 16750

      660
  • 13.2 Signal Descriptions

    661
    • Table 442. UART Signal Descriptions

      661
  • 13.3 Theory of Operation

    662
    • Figure 89. Example UART Data Frame

      662
    • Figure 90. NRZ Bit Encoding Example - (0100 1011)

      662
    • 13.3.1 FIFO Interrupt Mode Operation

      663
      • 13.3.1.1 Receiver Interrupt

        663
      • 13.3.1.2 Transmit Interrupt

        663
    • 13.3.2 Removing Trailing Bytes In Interrupt Mode

      664
      • 13.3.2.1 Character Time-out Interrupt

        664
    • 13.3.3 FIFO Polled Mode Operation

      664
      • 13.3.3.1 Receive Data Service

        664
      • 13.3.3.2 Transmit Data Service

        664
    • 13.3.4 Autoflow Control

      665
      • 13.3.4.1 RTS Autoflow

        665
      • 13.3.4.2 CTS Autoflow

        665
    • 13.3.5 Auto-Baud-Rate Detection

      666
      • Equation 17. Baud Rate Formula

        666
      • Table 443. Divisor Values for Typical Baud Rates

        666
    • 13.3.6 Manual Baud Rate Selection

      667
  • 13.4 Register Descriptions

    668
    • Table 444. UART Register Addresses as Offsets of a Base

      668
    • Table 445. UART Unit Registers

      668
    • Table 446. UART Register MMR Addresses

      669
    • 13.4.1 UART x Receive Buffer Register

      670
      • Table 447. UART x Receive Buffer Register - (UxRBR)

        670
    • 13.4.2 UART x Transmit Holding Register

      670
      • Table 448. UART x Transmit Holding Register - (UxTHR)

        670
    • 13.4.3 UART x Interrupt Enable Register

      671
      • Table 449. UART x Interrupt Enable Register - (UxIER)

        671
    • 13.4.4 UART x Interrupt Identification Register

      672
      • Table 450. UART x Interrupt Identification Register - (UxIIR)

        672
      • Table 451. Interrupt Identification Register Decode

        673
    • 13.4.5 UART x FIFO Control Register

      674
      • Table 452. UART x FIFO Control Register - (UxFCR) (Sheet 1 of 2)

        674
    • 13.4.6 UART x Line Control Register

      676
      • Table 453. UART x Line Control Register - (UxLCR) (Sheet 1 of 2)

        676
    • 13.4.7 UART x Modem Control Register

      678
      • Table 454. UART x Modem Control Register - (UxMCR) (Sheet 1 of 2)

        678
    • 13.4.8 UART x Line Status Register

      680
      • Table 455. UART x Line Status Register - (UxLSR) (Sheet 1 of 3)

        680
      • Table 456. UART x Modem Status Register

        683
      • Table 457. UART x Modem Status Register - (UxMSR)

        683
    • 13.4.9 UART x Scratchpad Register

      684
      • Table 458. UART x Scratchpad Register - (UxSCR)

        684
    • 13.4.10 Divisor Latch Registers

      685
      • Table 459. UART x Divisor Latch Low Register - (UxDLL)

        685
      • Table 460. UART x Divisor Latch High Register - (UxDLH)

        685
    • 13.4.11 UART x FIFO Occupancy Register

      686
      • Table 461. UART x FIFO Occupancy Register - (UxFOR)

        686
    • 13.4.12 UART x Auto-Baud Control Register

      687
      • Table 462. UART x Auto-Baud Control Register - (UxABR)

        687
    • 13.4.13 UART x Auto-Baud Count Register

      688
      • Table 463. UART x Auto-Baud Count Register - (UxACR)

        688
• 14.0 I2C Bus Interface Units

  689
  • 14.1 Overview

    689
  • 14.2 Theory of Operation

    690
    • Table 464. I2C Bus Definitions

      690
    • Figure 91. I2C Bus Configuration Example

      690
    • 14.2.1 Operational Blocks

      692
      • Figure 92. I2C Bus Interface Unit Block Diagram

        692
    • 14.2.2 I2C Bus Interface Modes

      694
      • Table 465. Modes of Operation

        694
    • 14.2.3 Start and Stop Bus States

      695
      • Table 466. START and STOP Bit Definitions

        695
      • Figure 93. Start and Stop Conditions

        695
      • 14.2.3.1 START Condition

        696
      • 14.2.3.2 No START or STOP Condition

        696
      • 14.2.3.3 STOP Condition

        696
        • Figure 94. START and STOP Conditions

          696
  • 14.3 I2C Bus Operation

    697
    • Equation 18. SCL Transition Period

      697
    • 14.3.1 Data and Addressing Management

      697
      • 14.3.1.1 Addressing a Slave Device

        698
        • Figure 95. Data Format of First Byte in Master Transaction

          698
    • 14.3.2 I2C Acknowledge

      699
      • Figure 96. Acknowledge on the I2C Bus

        699
    • 14.3.3 Arbitration

      700
      • 14.3.3.1 SCL Arbitration

        700
        • Figure 97. Clock Synchronization During the Arbitration Procedure

          700
      • 14.3.3.2 SDA Arbitration

        701
        • Figure 98. Arbitration Procedure of Two Masters

          701
    • 14.3.4 Master Operations

      702
      • Table 467. Master Transactions (Sheet 1 of 2)

        702
      • Figure 99. Master-Receiver Read from Slave-Transmitter

        704
      • Figure 100. Master-Receiver Read from Slave-Transmitter / Repeated Start /Master-Transmitter Write to Slave-Receiver

        704
      • Figure 101. A Complete Data Transfer

        704
    • 14.3.5 Slave Operations

      705
      • Table 468. Slave Transactions

        705
      • Figure 102. Master-Transmitter Write to Slave-Receiver

        706
      • Figure 103. Master-Receiver Read to Slave-Transmitter

        706
      • Figure 104. Master-Receiver Read to Slave-Transmitter, Repeated START, Master-Transmitter Write to Slave-Receiver

        706
    • 14.3.6 General Call Address

      707
      • Figure 105. General Call Address

        707
      • Table 469. General Call Address Second Byte Definitions

        707
  • 14.4 Slave Mode Programming Examples

    708
    • 14.4.1 Initialize Unit

      708
    • 14.4.2 Write 1 Byte as a Slave

      708
    • 14.4.3 Read 2 Bytes as a Slave

      708
  • 14.5 Master Programming Examples

    709
    • 14.5.1 Initialize Unit

      709
    • 14.5.2 Write 1 Byte as a Master

      709
    • 14.5.3 Read 1 Byte as a Master

      709
    • 14.5.4 Write 2 Bytes and Repeated Start Read 1 Byte as a Master

      710
    • 14.5.5 Read 2 Bytes as a Master - Send STOP Using the Abort

      711
  • 14.6 Glitch Suppression Logic

    712
  • 14.7 Reset Conditions

    713
  • 14.8 Register Definitions

    714
    • Table 470. I2C Register Summary

      714
    • 14.8.1 I2C Control Register x - ICRx

      715
      • Table 471. I2C Control Register x - ICRx (Sheet 1 of 2)

        715
    • 14.8.2 I2C Status Register x - ISRx

      717
      • Table 472. I2C Status Register x - ISRx (Sheet 1 of 2)

        717
    • 14.8.3 I2C Slave Address Register x - ISARx

      719
      • Table 473. I2C Slave Address Register x - ISARx

        719
    • 14.8.4 I2C Data Buffer Register x - IDBRx

      720
      • Table 474. I2C Data Buffer Register x - IDBRx

        720
    • 14.8.5 I2C Bus Monitor Register x - IBMRx

      721
      • Table 475. I2C Bus Monitor Register x - IBMRx

        721
    • 14.8.6 I2C Manual Bus Control Register x - IMBCRx

      722
      • Table 476. I2C Manual Bus Control Register x - IMBCRx

        722
• 15.0 General Purpose I/O Unit

  723
  • 15.1 General Purpose Input Output Support

    723
    • 15.1.1 General Purpose Inputs

      723
    • 15.1.2 General Purpose Outputs

      723
    • 15.1.3 Reset Initialization of General Purpose I/O Function

      723
  • 15.2 Register Definitions

    724
    • Table 477. General Purpose I/O Registers Addresses

      724
    • 15.2.1 GPIO Output Enable Register - GPOE

      725
      • Table 478. GPIO Output Enable Register - GPOE

        725
    • 15.2.2 GPIO Input Data Register - GPID

      726
      • Table 479. GPIO Input Data Register - GPID (Sheet 1 of 2)

        726
    • 15.2.3 GPIO Output Data Register - GPOD

      728
      • Table 480. GPIO Output Data Register - GPOD

        728
• 16.0 PMON Unit

  729
  • 16.1 PMON Counters

    729
  • 16.2 Overview

    729
    • Figure 106. Example Block Diagram of Component with Counter

      729
    • 16.2.1 Clock Counter Control

      730
      • Figure 107. Conceptual Diagram of Counter Array

        730
  • 16.3 Definitions

    731
    • Figure 108. Example Block Diagram of Single PMON Counter

      731
  • 16.4 Data Collection

    732
    • 16.4.1 Time Based Sampling

      732
      • Figure 109. Flowchart of Example Commands Sequence

        732
      • Table 481. Simple Time Based Counting of Events Example

        733
      • Figure 110. Block Diagram and Waveforms of Time Based Sampling Example

        733
    • 16.4.2 Hardware Event Based Control

      734
      • Table 482. Hardware Event Based Event Counting Example

        735
      • Figure 111. Block Diagram and Waveforms of Time Based Sampling Example

        735
    • 16.4.3 Incrementing By More Than 1

      736
      • Figure 112. Block Diagram & Waveforms of Time Based Sampling Example

        736
    • 16.4.4 Queue Analysis

      737
      • Table 483. Hardware Event Based Event Counting Example

        737
      • Figure 113. Block Diagram & Waveforms of Time Based Sampling Example

        737
      • Table 484. Queue Depth Histogram Example

        738
      • Table 485. Head of Queue Histogram Example

        739
      • Figure 114. Block Diagram of HOQ Histogram Example

        740
      • Figure 115. Waveforms of HOQ Histogram Example

        741
      • Figure 116. Processing of HOQ Histogram Example

        742
      • Figure 117. Output from HOQ Histogram Example

        742
  • 16.5 Non-Register-Based Interfaces

    743
    • 16.5.1 Events Input Port

      743
    • 16.5.2 Output Signals

      743
      • 16.5.2.1 Indicator Output

        744
        • Figure 118. Indicator Tree

          744
      • 16.5.2.2 Interrupt Output

        744
    • 16.5.3 Internal Bus Addresses

      745
      • Table 486. PMON Internal Bus Memory Mapped Register Range Offsets

        745
      • Table 487. PMON Register Summaries

        745
    • 16.5.4 PMON Feature Enable Register - PMONEN

      746
      • Table 488. PMON Feature Enable Register - PMONEN

        746
    • 16.5.5 PMON Status Register - PMONSTAT

      746
      • Table 489. PMON Status Register - PMONSTAT

        746
    • 16.5.6 PMON Memory Mapped Registers

      747
      • Table 490. PMON Internal Bus Memory Mapped Register Range Offsets

        747
      • Table 491. PMON Register Summaries

        748
      • 16.5.6.1 PMON Command Register 0-7 - PMON_CMD[0:7]

        749
        • Table 492. PMON Command Register 0-7 - PMON_CMD[0:7] (Sheet 1 of 4)

          749
      • 16.5.6.2 PMON Event Register 0-7 - PMON_EVR[0:7]

        753
        • Table 493. PMON Event Register 0-7 - PMON_EVR[0:7]

          753
      • 16.5.6.3 PMON Status Register 0-7 - PMON_STS[0:7]

        754
        • Table 494. PMON Status Register 0-7 - PMON_STS[0:7] (Sheet 1 of 2)

          754
      • 16.5.6.4 PMON Data Register 0-7 - PMON_DATA[0:7]

        756
        • Table 495. PMON DATA Register 7-0 - PMON_DATA[7:0]

          756
    • 16.5.7 PMON Events

      757
      • Table 496. Event Selection Code Summary

        757
      • 16.5.7.1 Null Event

        757
        • Table 497. Intel® 413808 and 413812 I/O Controllers in TPER Mode PMON Clock Events

          757
      • 16.5.7.2 Clock Events

        758
        • Table 498. Intel® 413808 and 413812 I/O Controllers PMON Clock Events

          758
      • 16.5.7.3 Threshold Events

        758
        • Table 499. Intel® 413808 and 413812 I/O Controllers PMON Threshold Events

          758
      • 16.5.7.4 PCI Interface Events

        759
        • Table 500. PCI Interface Events

          759
      • 16.5.7.5 PCI Express Interface Events

        760
        • Table 501. PCI Express Interface Summary

          760
      • 16.5.7.6 North Internal Bus Events

        761
        • Table 502. North Internal Bus Source Select Summary

          761
        • Table 503. North Internal Bus Initiator Events

          761
      • 16.5.7.7 South Internal Bus Events

        762
        • Table 504. South Internal Bus Source Select Summary

          762
        • Table 505. South Internal Bus Initiator Events

          762
• 17.0 Clocking and Reset

  763
  • 17.1 Clocking Overview

    763
    • Figure 119. Intel® 413808 and 413812 I/O Controllers in TPER Mode Clocking Regions Diagram

      763
    • 17.1.1 Clocking Theory of Operation

      764
      • 17.1.1.1 Clocking Region 1 (PCI Express)

        764
      • 17.1.1.2 Clocking Region 2 (PCI)

        764
        • 17.1.1.2.1 Central Resource Mode (PCIX_EP# = ‘1’)

          765
          • Table 506. PCI Bus Frequency Initialization

            765
          • Table 507. CR_FREQ[1:0] Encoding

            765
        • 17.1.1.2.2 cPCI Hot-Swap Mode (PCIX_EP# = ‘0’ and HS_SM# = ‘0’)

          766
          • Table 508. HS_FREQ Encoding

            766
        • 17.1.1.2.3 End Point Mode (PCIX_EP# = 0 and HS_SM# = 1)

          766
          • Table 509. PCI-X Initialization Pattern1

            766
        • 17.1.1.2.4 Secondary Clock Outputs

          767
          • Table 510. Secondary Clock Output Control

            767
      • 17.1.1.3 Clocking Region 3 (Internal Bus)

        768
      • 17.1.1.4 Clocking Region 4 (Peripheral Bus Interface)

        768
      • 17.1.1.5 Clocking Region 5

        768
      • 17.1.1.6 Clocking Region 7 (Intel XScale® Processor)

        768
    • 17.1.2 Clocking Region Summary

      769
      • Table 511. Clock Pin Summary

        769
  • 17.2 Reset Overview

    770
    • 17.2.1 Fundamental Reset

      770
    • 17.2.2 Software Reset

      771
    • 17.2.3 Secondary Bus Reset

      771
    • 17.2.4 PCI Reset

      772
    • 17.2.5 PCI Express Hot Reset

      772
    • 17.2.6 WARM_RST# Reset Mechanism

      772
    • 17.2.7 Intel XScale® Processor Reset Mechanism

      773
      • Table 512. Core Reset Control Bit Locations

        773
    • 17.2.8 Internal Bus Reset

      774
      • Table 513. Internal Bus Reset Control Bit Locations

        775
      • Table 514. Internal Bus Reset Summary (Sheet 1 of 2)

        775
  • 17.3 Reset Pins

    777
    • Table 515. Reset Pin Summary

      777
  • 17.4 Device Function Select

    778
    • Table 516. TPER Mode Per Function Storage Port Allocation (CONTROLLER_ONLY#=1)

      778
    • Table 517. Non-TPER Mode Per Function Storage Port Allocation (CONTROLLER_ONLY#=0)

      778
  • 17.5 Reset Strapping Options

    779
    • Table 518. Reset Strap Signals (Sheet 1 of 2)

      780
• 18.0 Test Logic Unit and Testability

  782
  • 18.1 Overview

    782
  • 18.2 IEEE 1149.1 Standard Test Access Port (TAP)

    783
    • Figure 120. IEEE 1149.1 Std. Block Diagram

      783
    • 18.2.1 TAP Pin Description

      784
      • 18.2.1.1 Test Clock (TCK)

        784
      • 18.2.1.2 Test Mode Select (TMS)

        784
      • 18.2.1.3 Test Data Input (TDI)

        784
      • 18.2.1.4 Test Data Output (TDO)

        784
      • 18.2.1.5 Asynchronous Reset (TRST#)

        784
    • 18.2.2 TAP Controller

      785
      • Figure 121. Timing of Actions in a TAP Controller State

        785
      • Figure 122. TAP Controller State Diagram

        785
      • 18.2.2.1 Test-Logic-Reset State

        786
      • 18.2.2.2 Run-Test/Idle State

        786
      • 18.2.2.3 Select-DR-Scan State

        786
      • 18.2.2.4 Capture-DR State

        786
      • 18.2.2.5 Shift-DR State

        787
      • 18.2.2.6 Exit1-DR State

        787
      • 18.2.2.7 Pause-DR State

        787
      • 18.2.2.8 Exit2-DR State

        787
      • 18.2.2.9 Update-DR State

        787
      • 18.2.2.10 Select-IR-Scan State

        788
      • 18.2.2.11 Capture-IR State

        788
      • 18.2.2.12 Shift-IR State

        788
      • 18.2.2.13 Exit1-IR State

        788
      • 18.2.2.14 Pause-IR State

        788
      • 18.2.2.15 Exit2-IR State

        789
      • 18.2.2.16 Update-IR State

        789
    • 18.2.3 TAP Controller Registers

      790
      • 18.2.3.1 Instruction Register

        790
      • 18.2.3.2 Instructions

        791
        • Table 519. TLU TAP Controller Instruction Set

          791
      • 18.2.3.3 Boundary-Scan Register

        792
      • 18.2.3.4 Bypass Register

        792
      • 18.2.3.5 Device Identification Register

        792
        • Figure 123. IOP Device ID Register

          792
        • Table 520. IOP Device ID Register Field Definitions

          792
        • Table 521. IOP Device ID Register Settings

          792
  • 18.3 Definition of Terms

    793
• 19.0 Peripheral Registers

  794
  • 19.1 Overview

    794
  • 19.2 Accessing Peripheral Memory-Mapped Registers

    795
  • 19.3 Accessing Peripheral Registers Using the Core Coprocessor Register Interface

    795
  • 19.4 Architecturally Reserved Memory Space

    795
  • 19.5 Default Memory Space Setup

    796
    • Figure 124. Intel® 413808 and 413812 I/O Controllers in TPER Mode Memory Address Space

      797
  • 19.6 Peripheral Memory-Mapped Register Address Space

    798
    • Table 522. PMMR Base Address Register (PMMRBAR) Default Value

      798
    • Table 523. Local Addresses for Integrated Peripherals (Sheet 1 of 3)

      798
    • 19.6.1 Internal Units

      801
      • 19.6.1.1 Peripheral Bus Interface Unit

        801
        • Table 524. PBI Base Address Offset.

          801
        • Table 525. Peripheral Bus Interface Unit

          801
      • 19.6.1.2 System Controller

        802
        • Table 526. SC Base Address Offset.

          802
        • Table 527. System Controller Unit

          802
      • 19.6.1.3 Internal Bus Bridge

        802
        • Table 528. Internal Bus Bridge Base Address Offset.

          802
        • Table 529. Internal Bus Bridge

          802
      • 19.6.1.4 I/O Pad Control

        803
        • Table 530. I/O Pad Control Base Address Offset.

          803
        • Table 531. I/O Pad Control Unit

          803
      • 19.6.1.5 UART 0-1

        804
        • Table 532. UART 0-1 Offset.

          804
        • Table 533. UART

          804
      • 19.6.1.6 GPIO

        805
        • Table 534. GPIO Offset.

          805
        • Table 535. GPIO

          805
      • 19.6.1.7 I2C Bus Interface Unit 0-2

        805
        • Table 536. I2C 0-2 Offset.

          805
        • Table 537. I2C Unit

          805
      • 19.6.1.8 Messaging Unit

        806
        • Table 538. Messaging Unit Offset.

          806
        • Table 539. Messaging Unit (Sheet 1 of 2)

          806
      • 19.6.1.9 PMON Unit

        808
        • Table 540. PMON Unit Base Address Offset.

          808
        • Table 541. PMON Unit

          808
    • 19.6.2 Host Interface Units

      809
      • Table 542. PCI Function MMR Locations

        809
      • 19.6.2.1 Address Translation Unit (PCI-X)

        810
        • Table 543. Intel® 413808 and 413812 I/O Controllers ATUX Configuration Space Base Address Offset

          810
        • Table 544. Address Translation Unit Registers - ATUX (Sheet 1 of 3)

          811
      • 19.6.2.2 Address Translation Unit (PCI-E)

        814
        • Table 545. Intel® 413808 and 413812 I/O Controllers ATUE Configuration Space Base Address Offset

          814
        • Table 546. Address Translation Unit Registers - ATUE (Sheet 1 of 4)

          815
  • 19.7 PCI Configuration Space

    819
    • Table 547. Intel® 413808 and 413812 I/O Controllers in TPER Mode PCI Function Visibility

      819
  • 19.8 Coprocessor Register Space

    819
    • Table 548. Coprocessor Registers Assigned to Integrated Peripherals

      819
    • Table 549. Coprocessor Register Locations (Sheet 1 of 4)

      820