Intel 413808 Manuel D’Utilisation

Intel

®

 413808 and 413812 I/O Controllers in TPER Mode

October 2007

Developer’s Manual

Order Number: 317805-001US

783

Test Logic Unit and Testability—Intel

®

 413808 and 413812

18.2

IEEE 1149.1 Standard Test Access Port (TAP)

The I/O processor contains test logic that is compatible with the IEEE Standard 

1149.1-2001 Test Access Port (TAP) and Boundary Scan Architecture. Logic that 

conforms to this standard contains:

• Test Access Port (TAP):

— four inputs (

TDI

, 

TMS

, 

TRST#

 and 

TCLK

)

— single output (

TDO

).

• TAP controller

• Instruction register

• Group of test data registers

Each of these is described in more detail below. 

 shows a generic diagram for 

logic conforming to the IEEE 1149.1 test standard.

Figure 120. IEEE 1149.1 Std. Block Diagram

TAP

Controller 

(16-State)

Boundary Scan Register

Device ID Register

Design-Specific Data Registers

Bypass Register

Instruction Decode

Shift Register

Internal Logic

MUX

MUX

Instruction Bits

Test Data Registers

Intstruction Registers

M

od

e1

M

od

e4

M

od

e3

M

od

e2

S

e

le

ct

TCK*

Select

Shift

Reset*

ClockIR

ShiftIR

UpdateIR

Reset*

ClockDR

ShiftDR

UpdateDR

TMS

TCK

Device Outputs

TDO

TDI

Device Inputs

TRST*

B6311-01