Intel 413808 Manuel D’Utilisation
Intel
®
413808 and 413812—Peripheral Registers
Intel
®
413808 and 413812 I/O Controllers in TPER Mode
Developer’s Manual
October 2007
812
Order Number: 317805-001US
Reserved
32
+084H
Reserved
32
+088H
Reserved
32
+08CH
VPD Capability Identifier Register — VPD_Cap_ID
8
+090H
VPD Next Item Pointer Register — VPD_Next_Item_Ptr
8
+091H
VPD Address Register — VPDAR
16
+092H
VPD Data Register — VPDDR
32
+094H
PM Capability Identifier Register — PM_Cap_ID
8
+098H
PM Next Item Pointer Register — PM_Next_Item_Ptr
8
+099H
ATU Power Management Capabilities Register — APMCR
16
+09AH
ATU Power Management Control/Status Register — APMCSR
16
+09CH
MSI_Capability Identifier Register — MSI_Cap_ID
8
+0A0H
MSI Next Item Pointer Register — MSI_Next_Item_Ptr
8
+0A1H
MSI Message Control Register — MSI_MCR
16
+0A2H
MSI Address Register — MSI_ADDR
32
+0A4H
MSI Message Upper Address Register — MSI_MUAR
32
+0A8H
MSI Message Data Register — MSI_MD
16
+0ACH
Reserved
16
+0AEH
MSI-X Capability Identifier Register — MSI-X_Cap_ID
8
+0B0H
MSI-X Next Item Pointer Register — MSI-X_Next_Item_Ptr
8
+0B1H
MSI-X Message Control Register — MSI-X_MCR
16
+0B2H
MSI-X Table Offset Register — MSI-X_Table_Offset
32
+0B4H
MSI-X Pending Bit Array Offset Register — MSI-X_PBA_Offset
32
+0B8H
MU MSI-X Control Register x — MMCRx
32
+0BCH
Reserved
x
+0C0H through 0CFH
PCI-X Capability Identifier Register — PCI-X_Cap_ID
8
+0D0H
PCI-X Next Item Pointer Register — PCI-X_Next_Item_Ptr
8
+0D1H
PCI-X Command Register — PCIXCMD
16
+0D2H
PCI-X Status Register — PCIXSR
32
+0D4H
ECC Control and Status Register — ECCCSR
32
+0D8H
ECC First Address Register — ECCFAR
32
+0DCH
ECC Second Address Register — ECCSAR
32
+0E0H
ECC Attribute Register — ECCAR
32
+0E4H
CompactPCI* Hot-Swap Capability ID Register
8
+0E8H
Offset EDh: HS_NXTP — Next Item Pointer
8
+0E9H
HS_CNTRL — Hot-Swap Control/Status Register
8
+0EAH
Reserved
x
+0EBH through 1FFH
Inbound ATU Base Address Register 3 — IABAR3
32
+200H
Inbound ATU Upper Base Address Register 3 — IAUBAR3
32
+204H
Inbound ATU Limit Register 3 — IALR3
32
+208H
Inbound ATU Translate Value Register 3 — IATVR3
32
+20CH
Inbound ATU Upper Translate Value Register 3 — IAUTVR3
32
+210H
Reserved
x
+214H through 2FFH
Outbound I/O Base Address Register — OIOBAR
32
+300H
Table 544. Address Translation Unit Registers — ATUX (Sheet 2 of 3)
Register Description (Name)
Register
Size in
Bits
Internal Bus Address Offset
(Relative to ATUX Base
Address Offset)
Notes:
1.
MSI and MSI-X Capability Registers are documented in the Messaging Unit Chapter.