Emerson ATCA-9305 Manuel D’Utilisation
3-1
Section 3
Cavium Processor Complex
The ATCA-9305 provides two Cavium processor complexes. The major devices on each
complex consist of the Cavium CN5860 processor, two StratixGX bridges, SDRAM,
RLDRAM®, an I
complex consist of the Cavium CN5860 processor, two StratixGX bridges, SDRAM,
RLDRAM®, an I
2
C EEPROM, socketed ROM, Flash, and the PCI bus interface.
Figure 3-1:
Cavium Processor Complex Block Diagram
CAVIUM CN5860 PROCESSOR
The main features of the CN5860 include:
Table 3-1:
CN5860 Features
Feature:
Description:
Processor Core
Up to 16 cnMIPS™ cores
Core Speed
Network Services Processor (NSP)
Network Services Processor (NSP)
up to 800 MHz, processing up to 30 million packets per second
System Packet Interface
Two SPI-4.2 ports
L2 Cache
2 MB, eight-way set associative
DRAM
144-bit DDR2 DRAM interface
RLDRAM
18-bit RLDRAM, low-latency memory direct access
PCI
64-bit, PCI 2.3 compatible
Console
(ENG use only)
PCI Bus
I2C
EEPROM
COP/
JTAG
BCM56802
XAUI 10 Gb
Switch
5 XAUI
XAUI 13
XAUI 14
PCI Bus
IDSEL13
6 XAUI
Console
(ENG use only)
Cavium
Octeon
CN5860
CN5860
Processor 1
SPI-1
PCI
Bus
IDSEL11
Serial 0
D1_DDR2
I2C
Serial 1
SPI-0
Stratix II GX
#2
RLDRAM
64MB
Local Bus
Addr/Data
COP/
JTAG
Serial CFG
EEPROM
RLDRAM
64MB
P1 DDR
SDRAM
SDRAM
P2 DDR2
SDRAM
RLDRAM
64MB
RLDRAM
64MB
I2C
EEPROM
RLDRAM
64MB
RLDRAM
64MB
RLDRAM
64MB
RLDRAM
64MB
Stratix II GX
#1
Stratix II GX
#4
I2C
I2C
Stratix II GX
#3
Cavium
Octeon
CN5860
CN5860
Processor 2
Serial 0
Serial 1
D1_DDR2
I2C
SPI-1
SPI-0
Local Bus
Addr/Data
PCI
Bus
IDSEL12
Bus
IDSEL12
Cavium Processor Complex 1
Cavium Processor Complex 2
NOR
Flash
4M x8
Socketed
ROM
512K x8
NOR
Flash
4M x8
Socketed
ROM
512K x8