Emerson ATCA-9305 Manuel D’Utilisation

5-1

Section 5

Management Processor CPLD

The ATCA-9305 uses a Programmable Logic Device (PLD) to provide control logic for the
local bus. The PLD implements various registers for reset, hardware, and LPC bus communi-
cation between the processors.

MPC8548 PLD REGISTER SUMMARY

The PLD registers start at address FC40,0000

. As a rule, registers retain their values

through all resets except for power-on and front panel reset.

Table 5-1

lists the 8-bit PLD reg-

isters followed by the register bit descriptions.

Table 5-1:

PLD Register Summary

Address
Offset (hex):

Mnemonic:

Register Name:

See Page:

0x00

PIDR

Product ID

5-2

0x04

HVR

Hardware Version

5-2

0x08

PVR

PLD Version

5-3

0x0C

PLLCR

PLL Configuration

5-3

0x10

HCR00

Hardware Configuration 0

5-4

0x18

JSR

Jumper Setting

5-4

0x1C

LEDR

LED

5-5

0x20

RER

Reset Event

5-5

0x24

RCR1

Reset Command #1

5-6

0x28

RCR2

Reset Command #2

5-6

0x2C

RCR3

Reset Command #3

5-6

0x30

RCR4

Reset Command #4

5-7

0x34

RCR5

Reset Command #5

5-7

0x38

RCRS1

Reset Command Sticky #1

5-8

0x3C

RCRS2

Reset Command Sticky #2

5-8

0x40

SCR1

Scratch #1

—

0x50

BDRR

Boot Device Redirection

5-9

0x54

MISC

Miscellaneous Control (SIO, I2C, Test Clock)

5-9

0x58

LFTR1

Low Frequency Timer 1

5-9

0x5C

LFTR2

Low Frequency Timer 2

5-9

0x60

RGSR

RTM GPIO State

5-10

0x64

RGCR

RTM GPIO Control

5-10

0x68

RTMCR

RTM Control

5-11

0x70

CMUL1

Cavium 1 C_MUL Clock Divisor Control

5-11

0x74

CMUL2

Cavium 2 C_MUL Clock Divisor Control

5-12

0x78

JTAG

Altera JTAG Chain Software Control

5-12

0x80

CGCR

Cavium GPIO Control

5-12