Emerson 752I Manuel D’Utilisation
System Controller:
CPU Interface
5-2
Figure 5-1:
MV64460 Block Diagram
CPU INTERFACE
CPU interface features include:
• 32-bit address and 64-bit data buses
• Support for Symmetrical Multi-Processing (SMP) in both 60x and MPX bus modes
• Support for up to four slave devices on the same 60x bus
• Up to 200 MHz CPU bus frequency
• CPU address remapping to PCI
• Support for access, write, and cache protection to a configurable address range
• Support for up to 16 pipelined address transactions
The Katana
752i monitor configures the MV64460 controller so that it provides these 32-
bit registers to the PowerPC processor in the correct byte order (assuming the access width
is 32 bits). The CPU setting of the CPU Configuration register affects the MV64460 behavior
on subsequent CPU accesses. This register activates with transactions pipeline disabled. In
order to gain the maximum CPU interface performance, change this default by following
these steps:
is 32 bits). The CPU setting of the CPU Configuration register affects the MV64460 behavior
on subsequent CPU accesses. This register activates with transactions pipeline disabled. In
order to gain the maximum CPU interface performance, change this default by following
these steps:
CPU at up to 200 MHz
10/100/1000
72-bit at up to
200 MHz
SCC, TWSI
64-bit at 33/66 MHz
CPU Interface
+ 2 Mb SRAM
4 DMA
2 XOR
GPIO, SCC,
TWSI, Int,
Timers
PCI
DDR
PCI
Device
32-bit at
66 MHz
64-bit at 33/66 MHz
3 Ports Gb
Ethernet +
FIFO Interface