Emerson 752I Manuel D’Utilisation
System Controller:
Internal (IDMA) Controller
5-4
INTERNAL (IDMA) CONTROLLER
Each of the four DMA engines can move data between any source and any destination, such
as the SDRAM, device, PCI_0, or CPU bus. These engines optimize system performance by
moving large amounts of data without significant CPU intervention. Read and write are
handled independently and concurrently.
as the SDRAM, device, PCI_0, or CPU bus. These engines optimize system performance by
moving large amounts of data without significant CPU intervention. Read and write are
handled independently and concurrently.
TIMER/COUNTERS
Each of the four 32-bit wide timer/counters can be selected to operate as a timer or a
counter. Each timer/counter increments with every Tclk rising edge. In counter mode, the
counter counts down to terminal count, stops, and issues an interrupt. In timer mode, the
timer counts down, issues an interrupt on terminal count, reloads itself to the programmed
value, and continues to count. Reads from the counter or timer are completed directly from
the counter, and writes are to the timer/counter register.
counter. Each timer/counter increments with every Tclk rising edge. In counter mode, the
counter counts down to terminal count, stops, and issues an interrupt. In timer mode, the
timer counts down, issues an interrupt on terminal count, reloads itself to the programmed
value, and continues to count. Reads from the counter or timer are completed directly from
the counter, and writes are to the timer/counter register.
PCI INTERFACE
The MV64460 supports two 64-bit PCI interfaces, which comply with the PCI Local Bus Spec-
ification revision 2.3. Other features include:
ification revision 2.3. Other features include:
• Supports P2P memory, I/O, and configuration transactions
• PCI bus speed up to 66 MHz with zero wait states
• Operates either synchronous or asynchronous to CPU clock; at slower, equal, or faster
clock frequency
• 32/64-bit PCI master and target operations
For the Katana
752i, PCI1 is a 32-bit, 33/66MHz local PCI bus interface.
PCI_0 is a 32/64-bit, 33/66MHz cPCI bus interface.
PCI Configuration Space
The PCI slave supports Type 00 configuration space header as defined in the PCI specifica-
tion. The MV64460 is a multi-function device and the header is implemented in all eight
functions. The PCI interface implements the configuration header and this space is accessi-
ble from the CPU or PCI bus.
tion. The MV64460 is a multi-function device and the header is implemented in all eight
functions. The PCI interface implements the configuration header and this space is accessi-
ble from the CPU or PCI bus.