Epson ARM720T Manuel D’Utilisation

When multiple exceptions arise at the same time, a fixed priority system determines the order 

in which they are handled: 

1

Reset (highest priority).

2

Data Abort.

3

FIQ.

4

IRQ.

5

Prefetch  Abort.

6

Undefined Instruction, SWI (lowest priority).

Undefined Instruction and SWI are mutually exclusive, because they each correspond to 

particular (non-overlapping) decodings of the current instruction.
If a Data Abort occurs at the same time as an FIQ, and FIQs are enabled, the CPSR F flag is 

clear, the ARM720T processor enters the Data Abort handler and then immediately proceeds 

to the FIQ vector. A normal return from FIQ causes the Data Abort handler to resume 

execution. Placing Data Abort at a higher priority than FIQ is necessary to ensure that the 

transfer error does not escape detection. The time for this exception entry must be added to 

worst-case FIQ latency calculations.