Epson ARM720T Manuel D’Utilisation

The ARM720T processor provides a mechanism, 

Fast Context Switch Extension

 (FCSE), to 

translate virtual addresses to physical addresses based on the current value of the FCSE 

Process IDentifier

 (PID).

The virtual address produced by the processor core going to the IDC and MMU can be 

relocated if it lies in the bottom 32MB of the virtual address. That is, virtual address bits 

[31:25] = b0000000 by the substitution of the seven bits [31:25] of the FCSE PID register in 

the CP15 coprocessor. 
A change to the FCSE PID exhibits similar behavior to a delayed branch if:

•

the two instructions fetched immediately following an instruction to change the 

FCSE PID are fetched with a relocation to the previous FCSE PID

•

the addresses of the instructions being fetched lie within the range of addresses to 

be relocated.

On reset, the FCSE PID register bits [31:25] are set to b0000000, disabling all relocation. For 

this reason, the low address reset exception vector is effectively never relocated by this 

mechanism. 

All addresses produced by the processor core undergo this translation if they lie in 

the appropriate address range. This includes the exception vectors if they are 

configured to lie in the bottom of the virtual memory map. This configuration is 

determined by the V bit in the CP15 Control Register c1.