Nxp Semiconductors UM10310 Manuel D’Utilisation

UM10310_1

© NXP B.V. 2008. All rights reserved.

 

 

[1]

x = A, B, C, D

[2]

‘ON’ means in the CCUCLK cycle after the event takes place.

When the OCRx registers are written, a built in mechanism ensures that the value is not 
updated in the middle of a PWM pulse. This could result in an odd-length pulse. When the 
registers are written, the values are placed in two shadow registers, as is the case in basic 
timer operation mode. Writing to TCOU2 will cause the contents of the shadow registers 
to be updated on the next CCU Timer overflow. If OCRxH and/or OCRxL are read before 
the value is updated, the most currently written value is read. 

Setting the HLTEN bit in TCR20 enables the PWM Halt Function. When halt function is 
enabled, a capture event as enabled for the Input Capture A pin will immediately stop all 
activity on the PWM pins and set them to a predetermined state defined by FCOx bit. In 
PWM Mode, the FCOx bits in the CCCRx register hold the value the pin is forced to during 
halt. The value of the setting can be read back. The capture function and the interrupt will 

0

0

Output compare disabled. On power-on, this is the default state, and pins 
are configured as inputs.

0

1

Set when compare in 
operation. Cleared on 
compare match.

Non-Inverted PWM. Set 
on compare match. 
Cleared on CCU Timer 
underflow.

Non-Inverted PWM. 
Cleared on compare 
match, upcounting. Set 
on compare match, 
downcounting.

1

0

invalid configuration

1

1

Toggles on compare 
match

Inverted PWM. Cleared 
on compare match. Set 
on CCU Timer 
underflow.

Inverted PWM. Set on 
compare match, 
upcounting. Cleared on 
compare match, 
downcounting.