Manuel D’UtilisationTable des matières1. Introduction31.1 Pin configuration31.2 Pin description51.3 Functional diagram81.4 Block diagram91.5 Special function registers101.6 Memory organization202. Clocks212.1 Enhanced CPU212.2 Clock definitions212.2.1 Oscillator Clock (OSCCLK)212.3 External crystal oscillator option212.3.1 Low speed oscillator option212.3.2 Medium speed oscillator option222.3.3 High speed oscillator option222.4 Clock output222.5 On-chip RC oscillator option222.6 Watchdog oscillator option232.7 External clock input option232.8 Clock sources switch on the fly242.9 Oscillator Clock (OSCCLK) wake-up delay252.10 CPU Clock (CCLK) modification: DIVM register252.11 Low power select253. Interrupts253.1 Interrupt priority structure263.2 External Interrupt pin glitch suppression274. I/O ports284.1 Port configurations294.2 Quasi-bidirectional output configuration294.3 Open drain output configuration304.4 Input-only configuration314.5 Push-pull output configuration314.6 Port 0 and Analog Comparator functions314.7 Additional port features325. Power monitoring functions335.1 Brownout detection335.2 Power-on detection345.3 Power reduction modes346. Reset376.1 Reset vector387. Timers 0 and 1397.1 Mode 0407.2 Mode 1407.3 Mode 2417.4 Mode 3417.5 Mode 6417.6 Timer overflow toggle output438. Real-time clock system timer438.1 Real-time clock source448.2 Changing RTCS1/RTCS0458.3 Real-time clock interrupt/wake-up458.3.1 Real-time clock read back458.4 Reset sources affecting the Real-time clock459. Capture/Compare Unit (CCU)479.1 CCU Clock (CCUCLK)479.2 CCU Clock prescaling479.3 Basic timer operation489.4 Output compare509.5 Input capture519.6 PWM operation529.7 Alternating output mode539.8 Synchronized PWM register update549.9 HALT549.10 PLL operation559.11 CCU interrupt structure5610. UART5910.1 Mode 05910.2 Mode 15910.3 Mode 25910.4 Mode 36010.5 SFR space6010.6 Baud Rate generator and selection6010.7 Updating the BRGR1 and BRGR0 SFRs6010.8 Framing error6110.9 Break detect6110.10 More about UART Mode 06310.11 More about UART Mode 16410.12 More about UART Modes 2 and 36510.13 Framing error and RI in Modes 2 and 3 with SM2 = 16510.14 Break detect6610.15 Double buffering6610.16 Double buffering in different modes6610.17 Transmit interrupts with double buffering enabled (Modes 1, 2, and 3)6610.18 The 9th bit (bit 8) in double buffering (Modes 1, 2, and 3)6710.19 Multiprocessor communications6810.20 Automatic address recognition6911. I2C interface7011.1 I2C data register7111.2 I2C slave address register7111.3 I2C control register7211.4 I2C Status register7311.5 I2C SCL duty cycle registers I2SCLH and I2SCLL7311.6 I2C operation modes7411.6.1 Master Transmitter mode7411.6.2 Master Receiver mode7511.6.3 Slave Receiver mode7611.6.4 Slave Transmitter mode7712. Serial Peripheral Interface (SPI)8412.1 Configuring the SPI8812.2 Additional considerations for a slave8912.3 Additional considerations for a master8912.4 Mode change on SS8912.5 Write collision9012.6 Data mode9012.7 SPI clock prescaler select9413. Analog comparators9413.1 Comparator configuration9413.2 Internal reference voltage9613.3 Comparator input pins9613.4 Comparator interrupt9613.5 Comparators and power reduction modes9713.6 Comparators configuration example9713.7 Programmable Gain Amplifier (PGA)9814. Keypad interrupt (KBI)10015. Watchdog timer (WDT)10115.1 Watchdog function10115.2 Feed sequence10215.3 Watchdog clock source10515.4 Watchdog Timer in Timer mode10615.5 Power-down operation10715.6 Periodic wake-up from power-down without an external oscillator10716. Additional features10716.1 Software reset10816.2 Dual Data Pointers10817. Data EEPROM10917.1 Data EEPROM read11017.2 Data EEPROM write11017.3 Hardware reset11117.4 Multiple writes to the DEEDAT register11117.5 Sequences of writes to DEECON and DEEDAT registers11117.6 Data EEPROM Row Fill11117.7 Data EEPROM Block Fill11218. Flash memory11218.1 General description11218.2 Features11218.3 Flash programming and erase11318.4 Using Flash as data storage: IAP-Lite11318.5 In-circuit programming (ICP)11718.6 ISP and IAP capabilities of the P89LPC932111718.7 Boot ROM11718.8 Power on reset code execution11718.9 Hardware activation of Boot Loader11818.10 In-system programming (ISP)11818.11 Using the In-system programming (ISP)11918.12 In-application programming (IAP)12218.13 IAP authorization key12218.14 Flash write enable12218.15 Configuration byte protection12318.16 IAP error status12318.17 User configuration bytes12718.18 User security bytes12818.19 Boot Vector register12918.20 Boot status register12919. Instruction set13120. Legal information13420.1 Definitions13420.2 Disclaimers13420.3 Trademarks13421. Tables13522. Figures13723. Contents138Taille: 790 koPages: 139Language: EnglishOuvrir le manuel