Emerson RTM-ATCA-7350 Manuel D’Utilisation
P32 Pinout
Controls, LEDs and Connectors
RTM-ATCA-7350 Installation and Use (6806800H30F)
45
3.3.3
P32 Pinout
P32 is used for port1 and port4 signals of the Fabric interface, and the PCIE signals from front
board.
board.
PinA1 on the server board side is on the top of the connector, and on the left column of the P32
connector while the server board is placed top side upwards and the front panel is on the left.
connector while the server board is placed top side upwards and the front panel is on the left.
8
RTM_EXP7_R
XP2
XP2
RTM_EXP7_RXN
2
2
GND
MCH_EXP7_R
XP1
XP1
MCH_EXP7_RX
N1
N1
GND
9
RTM_EXP7_R
XP1
XP1
RTM_EXP7_RXN
1
1
GND
MCH_EXP7_R
XP0
XP0
MCH_EXP7_RX
N0
N0
GND
10
RTM_EXP7_R
XP0
XP0
RTM_EXP7_RXN
0
0
GND
RTM_PCIE7_
CLK_P
CLK_P
RTM_PCIE7_CL
K_N
K_N
GND
Table 3-5 PIN 31 Pinout (continued)
ZD1
A
B
C
D
Table 3-6 PIN 32 Pinout
ZD2
A
B
C
D
E
F
G
H
1
RTM_P
E_SDA
E_SDA
RTM_P
E_SCL
E_SCL
GN
D
D
MCH_E
XP6_R
XP1
XP6_R
XP1
MCH_E
XP6_R
XN1
XP6_R
XN1
GN
D
D
RTM_E
XP6_R
XP3
XP6_R
XP3
RTM_E
XP6_R
XN3
XP6_R
XN3
GN
D
D
MCH_E
XP6_R
XP3
XP6_R
XP3
MCH_E
XP6_R
XN3
XP6_R
XN3
GN
D
D
2
RTM_E
XP6_R
XP1
XP6_R
XP1
RTM_E
XP6_R
XN1
XP6_R
XN1
GN
D
D
MCH_E
XP6_R
XP0
XP6_R
XP0
MCH_E
XP6_R
XN0
XP6_R
XN0
GN
D
D
RTM_E
XP6_R
XP2
XP6_R
XP2
RTM_E
XP6_R
XN2
XP6_R
XN2
GN
D
D
MCH_E
XP6_R
XP2
XP6_R
XP2
MCH_E
XP6_R
XN2
XP6_R
XN2
GN
D
D
3
RTM_E
XP6_R
XP0
XP6_R
XP0
RTM_E
XP6_R
XN0
XP6_R
XN0
GN
D
D
RTM_P
CIE6_C
LK_P
CIE6_C
LK_P
RTM_P
CIE6_C
LK_N
CIE6_C
LK_N
GN
D
D
RTM_E
XP5_R
XP3
XP5_R
XP3
RTM_E
XP5_R
XN3
XP5_R
XN3
GN
D
D
MCH_E
XP5_R
XP3
XP5_R
XP3
MCH_E
XP5_R
XN3
XP5_R
XN3
GN
D
D
4
RTM_E
XP5_R
XP1
XP5_R
XP1
RTM_E
XP5_R
XN1
XP5_R
XN1
GN
D
D
MCH_E
XP5_R
XP1
XP5_R
XP1
MCH_E
XP5_R
XN1
XP5_R
XN1
GN
D
D
RTM_E
XP5_R
XP2
XP5_R
XP2
RTM_E
XP5_R
XN2
XP5_R
XN2
GN
D
D
MCH_E
XP5_R
XP2
XP5_R
XP2
MCH_E
XP5_R
XN2
XP5_R
XN2
GN
D
D
5
RTM_E
XP5_R
XP0
XP5_R
XP0
RTM_E
XP5_R
XN0
XP5_R
XN0
GN
D
D
MCH_E
XP5_R
XP0
XP5_R
XP0
MCH_E
XP5_R
XN0
XP5_R
XN0
GN
D
D
RTM_P
CIE4_C
LK_P
CIE4_C
LK_P
RTM_P
CIE4_C
LK_N
CIE4_C
LK_N
GN
D
D
RTM_P
CIE5_C
LK_P
CIE5_C
LK_P
RTM_P
CIE5_C
LK_N
CIE5_C
LK_N
GN
D
D
6
RTM_E
XP4_R
XP1
XP4_R
XP1
RTM_E
XP4_R
XN1
XP4_R
XN1
GN
D
D
MCH_E
XP4_R
XP1
XP4_R
XP1
MCH_E
XP4_R
XN1
XP4_R
XN1
GN
D
D
RTM_E
XP4_R
XP3
XP4_R
XP3
RTM_E
XP4_R
XN3
XP4_R
XN3
GN
D
D
MCH_E
XP4_R
XP3
XP4_R
XP3
MCH_E
XP4_R
XN3
XP4_R
XN3
GN
D
D
7
RTM_E
XP4_R
XP0
XP4_R
XP0
RTM_E
XP4_R
XN0
XP4_R
XN0
GN
D
D
MCH_E
XP4_R
XP0
XP4_R
XP0
MCH_E
XP4_R
XN0
XP4_R
XN0
GN
D
D
RTM_E
XP4_R
XP2
XP4_R
XP2
RTM_E
XP4_R
XN2
XP4_R
XN2
GN
D
D
MCH_E
XP4_R
XP2
XP4_R
XP2
MCH_E
XP4_R
XN2
XP4_R
XN2
GN
D
D
8
RTM_P
E6_PR
SNT_R
_
E6_PR
SNT_R
_
RTM_P
E5_PR
SNT_R
_
E5_PR
SNT_R
_
GN
D
D
RTM_P
E4_PR
SNT_
E4_PR
SNT_
RTM_P
E5_WA
KE_
E5_WA
KE_
GN
D
D
RTM_P
E6_RS
T_
E6_RS
T_
RTM_P
E5_RS
T_
E5_RS
T_
GN
D
D
RTM_P
E4_RS
T_
E4_RS
T_
RTM_P
E4_WA
KE_
E4_WA
KE_
GN
D
D
9
RTM_F
C2_TX3
_H
C2_TX3
_H
RTM_F
C2_TX3
_L
C2_TX3
_L
GN
D
D
RTM_F
C1_TX3
_H
C1_TX3
_H
RTM_F
C1_TX3
_L
C1_TX3
_L
GN
D
D
RTM_F
C2_TX0
_H
C2_TX0
_H
RTM_F
C2_TX0
_L
C2_TX0
_L
GN
D
D
RTM_F
C1_TX0
_H
C1_TX0
_H
RTM_F
C1_TX0
_L
C1_TX0
_L
GN
D
D