Intel D425 AU80610006252AA Manuel D’Utilisation
Codes de produits
AU80610006252AA
Processor Configuration Registers
Datasheet
119
Bit Access Default
Value
Description
9:8 RO 0h
GTT Graphics Memory Size (GGMS):
This field is used to select the amount of Main
Memory that is pre-allocated to support the
Internal Graphics Translation Table. The BIOS
ensures that memory is pre-allocated only when
Internal graphics is enabled.
00: No memory pre-allocated. GTT cycles (Mem
and IO) are not claimed.
01: 1 MB of memory pre-allocated for GTT.
10: Reserved
11: Reserved
Note: This register is locked and becomes Read
Only when the D_LCK bit in the SMRAM register
is set.
This field is used to select the amount of Main
Memory that is pre-allocated to support the
Internal Graphics Translation Table. The BIOS
ensures that memory is pre-allocated only when
Internal graphics is enabled.
00: No memory pre-allocated. GTT cycles (Mem
and IO) are not claimed.
01: 1 MB of memory pre-allocated for GTT.
10: Reserved
11: Reserved
Note: This register is locked and becomes Read
Only when the D_LCK bit in the SMRAM register
is set.
7:4 RO 0011b
Graphics Mode Select (GMS):
This field is used to select the amount of Main
Memory that is pre-allocated to support the
Internal Graphics device in VGA (non-linear) and
Native (linear) modes. The BIOS ensures that
memory is pre-allocated only when Internal
graphics is enabled.
0000: No memory pre-allocated. Device 2 (IGD)
does not claim VGA cycles (Mem and IO), and
the Sub-Class Code field within Device 2
function 0 Class Code register is 80.
0001: DVMT (UMA) mode, 1 MB of memory
pre-allocated for frame buffer.
0011: DVMT (UMA) mode, 8 MB of memory
pre-allocated for frame buffer.
This field is used to select the amount of Main
Memory that is pre-allocated to support the
Internal Graphics device in VGA (non-linear) and
Native (linear) modes. The BIOS ensures that
memory is pre-allocated only when Internal
graphics is enabled.
0000: No memory pre-allocated. Device 2 (IGD)
does not claim VGA cycles (Mem and IO), and
the Sub-Class Code field within Device 2
function 0 Class Code register is 80.
0001: DVMT (UMA) mode, 1 MB of memory
pre-allocated for frame buffer.
0011: DVMT (UMA) mode, 8 MB of memory
pre-allocated for frame buffer.
NOTE: This register is locked and becomes
Read Only when the D_LCK bit in the
SMRAM register is set.
SMRAM register is set.
BIOS Requirement: BIOS must not set this field
to 000 if IVD (bit 1 of this register) is 0.
to 000 if IVD (bit 1 of this register) is 0.
3:2 RO 00b
Reserved ():
1 RO 0b
IGD VGA Disable (IVD):
0: Enable. Device 2 (IGD) claims VGA memory
and IO cycles, the Sub-Class Code within Device
2 Class Code register is 00.
1: Disable. Device 2 (IGD) does not claim VGA
cycles (Mem and IO), and the Sub- Class Code
field within Device 2 function 0 Class Code
register is 80.
BIOS Requirement: BIOS must not set this bit to
0 if the GMS field (bits 6:4 of this register) pre-
allocates no memory. This bit MUST be set to 1
if Device 2 is disabled.
0: Enable. Device 2 (IGD) claims VGA memory
and IO cycles, the Sub-Class Code within Device
2 Class Code register is 00.
1: Disable. Device 2 (IGD) does not claim VGA
cycles (Mem and IO), and the Sub- Class Code
field within Device 2 function 0 Class Code
register is 80.
BIOS Requirement: BIOS must not set this bit to
0 if the GMS field (bits 6:4 of this register) pre-
allocates no memory. This bit MUST be set to 1
if Device 2 is disabled.
0 RO 0b
Reserved ():