Manuels d'utilisation pour Intel D425

Table des matières

• I

  2
• 1 Processor Configuration Registers

  8
  • 1.1 Register Terminology

    8
  • 1.2 System Address Map

    10
    • 1.2.1 Legacy Address Range

      12
    • 1.2.2 Main Memory Address Range (1 MB - TOLUD)

      15
    • 1.2.3 PCI* Memory Address Range (TOLUD - 4 GB)

      18
    • 1.2.4 Main Memory Address Space (4 GB to TOUUD)

      20
    • 1.2.5 PCI Express Configuration Address Space

      21
    • 1.2.6 Graphics Memory Address Ranges

      22
    • 1.2.7 System Management Mode (SMM)

      22
    • 1.2.8 Memory Shadowing

      25
    • 1.2.9 I/O Address Space

      25
    • 1.2.10 Memory Controller Decode Rules and Cross-Bridge Address Mapping

      26
  • 1.3 Processor Register Introduction

    26
  • 1.4 I/O Mapped Registers

    27
  • 1.5 PCI Device 0

    28
    • 1.5.1 VID - Vendor Identification

      30
    • 1.5.2 DID - Device Identification

      31
    • 1.5.3 PCICMD - PCI Command

      31
    • 1.5.4 PCISTS - PCI Status

      33
    • 1.5.5 RID - Revision Identification

      35
    • 1.5.6 CC - Class Code

      35
    • 1.5.7 MLT - Master Latency Timer

      36
    • 1.5.8 HDR - Header Type

      36
    • 1.5.9 SVID - Subsystem Vendor Identification

      36
    • 1.5.10 SID - Subsystem Identification

      37
    • 1.5.11 CAPPTR - Capabilities Pointer

      37
    • 1.5.12 PXPEPBAR - PCI Express Egress Port Base Address

      37
    • 1.5.13 MCHBAR - GMCH Memory Mapped Register Range Base

      38
    • 1.5.14 GGC - GMCH Graphics Control Register

      39
    • 1.5.15 DEVEN - Device Enable

      41
    • 1.5.16 PCIEXBAR - PCI Express Register Range Base Address

      42
    • 1.5.17 DMIBAR - Root Complex Register Range Base Address

      44
    • 1.5.18 PAM0 - Programmable Attribute Map 0

      44
    • 1.5.19 PAM1 - Programmable Attribute Map 1

      46
    • 1.5.20 PAM2 - Programmable Attribute Map 2

      47
    • 1.5.21 PAM3 - Programmable Attribute Map 3

      48
    • 1.5.22 PAM4 - Programmable Attribute Map 4

      49
    • 1.5.23 PAM5 - Programmable Attribute Map 5

      50
    • 1.5.24 PAM6 - Programmable Attribute Map 6

      51
    • 1.5.25 LAC - Legacy Access Control

      52
    • 1.5.26 REMAPBASE - Remap Base Address Register

      52
    • 1.5.27 REMAPLIMIT - Remap Limit Address Register

      53
    • 1.5.28 SMRAM - System Management RAM Control

      53
    • 1.5.29 ESMRAMC - Extended System Management RAM Control

      55
    • 1.5.30 TOM - Top of Memory

      56
    • 1.5.31 TOUUD - Top of Upper Usable Dram

      57
    • 1.5.32 GBSM - Graphics Base of Stolen Memory

      57
    • 1.5.33 BGSM - Base of GTT stolen Memory

      58
    • 1.5.34 TSEGMB - TSEG Memory Base

      59
    • 1.5.35 TOLUD - Top of Low Usable DRAM

      59
    • 1.5.36 ERRSTS - Error Status

      61
    • 1.5.37 ERRCMD - Error Command

      62
    • 1.5.38 SMICMD - SMI Command

      63
    • 1.5.39 SKPD - Scratchpad Data

      64
    • 1.5.40 CAPID0 - Capability Identifier

      64
  • 1.6 MCHBAR

    66
    • 1.6.1 CHDECMISC - Channel Decode Misc

      67
    • 1.6.2 C0DRB0 - Channel 0 DRAM Rank Boundary Address 0

      68
    • 1.6.3 C0DRB1 - Channel 0 DRAM Rank Boundary Address 1

      69
    • 1.6.4 C0DRB2 - Channel 0 DRAM Rank Boundary Address 2

      69
    • 1.6.5 C0DRB3 - Channel 0 DRAM Rank Boundary Address 3

      70
    • 1.6.6 C0DRA01 - Channel 0 DRAM Rank 0,1 Attribute

      70
    • 1.6.7 C0DRA23 - Channel 0 DRAM Rank 2, 3 Attribute

      72
    • 1.6.8 C0CYCTRKPCHG - Channel 0 CYCTRK PCHG

      72
    • 1.6.9 C0CYCTRKACT - Channel 0 CYCTRK ACT

      73
    • 1.6.10 C0CYCTRKWR - Channel 0 CYCTRK WR

      74
    • 1.6.11 C0CYCTRKRD - Channel 0 CYCTRK READ

      75
    • 1.6.12 C0CYCTRKREFR - Channel 0 CYCTRK REFR

      76
    • 1.6.13 C0CKECTRL - Channel 0 CKE Control

      76
    • 1.6.14 C0REFRCTRL - Channel 0 DRAM Refresh Control

      78
    • 1.6.15 C0ODTCTRL - Channel 0 ODT Control

      80
    • 1.6.16 PMSTS - Power Management Status

      81
  • 1.7 DMIBAR

    82
    • 1.7.1 DMIVCECH - DMI Virtual Channel Enhanced Capability

      83
    • 1.7.2 DMIPVCCAP1 - DMI Port VC Capability Register 1

      84
    • 1.7.3 DMIPVCCAP2 - DMI Port VC Capability Register 2

      85
    • 1.7.4 DMIPVCCTL - DMI Port VC Control

      85
    • 1.7.5 DMIVC0RCAP - DMI VC0 Resource Capability

      86
    • 1.7.6 DMIVC0RCTL0 - DMI VC0 Resource Control

      86
    • 1.7.7 DMIVC0RSTS - DMI VC0 Resource Status

      87
    • 1.7.8 DMIVC1RCAP - DMI VC1 Resource Capability

      88
    • 1.7.9 DMIVC1RCTL1 - DMI VC1 Resource Control

      89
    • 1.7.10 DMIVC1RSTS - DMI VC1 Resource Status

      90
    • 1.7.11 DMIRCLDECH - DMI Root Complex Link Declaration

      91
    • 1.7.12 DMIESD - DMI Element Self Description

      91
    • 1.7.13 DMILE1D - DMI Link Entry 1 Description

      92
    • 1.7.14 DMILE1A - DMI Link Entry 1 Address

      93
    • 1.7.15 DMILE2D - DMI Link Entry 2 Description

      94
    • 1.7.16 DMILE2A - DMI Link Entry 2 Address

      95
    • 1.7.17 DMIRCILCECH - DMI Root Complex Internal Link Control

      95
    • 1.7.18 DMILCAP - DMI Link Capabilities

      96
    • 1.7.19 DMILCTL - DMI Link Control

      97
    • 1.7.20 DMILSTS - DMI Link Status

      98
  • 1.8 EPBAR

    98
    • 1.8.1 EPESD - EP Element Self Description

      99
    • 1.8.2 EPLE1D - EP Link Entry 1 Description

      100
    • 1.8.3 EPLE1A - EP Link Entry 1 Address

      101
    • 1.8.4 EPLE2D - EP Link Entry 2 Description

      101
    • 1.8.5 EPLE2A - EP Link Entry 2 Address

      102
  • 1.9 PCI Device 2 Function 0

    102
    • 1.9.1 VID2 - Vendor Identification

      105
    • 1.9.2 DID - Device Identification

      105
    • 1.9.3 PCICMD2 - PCI Command

      106
    • 1.9.4 PCISTS2 - PCI Status

      107
    • 1.9.5 RID2 - Revision Identification

      108
    • 1.9.6 CC - Class Code

      109
    • 1.9.7 CLS - Cache Line Size

      109
    • 1.9.8 MLT2 - Master Latency Timer

      110
    • 1.9.9 HDR2 - Header Type

      110
    • 1.9.10 MMADR - Memory Mapped Range Address

      110
    • 1.9.11 IOBAR - I/O Base Address

      111
    • 1.9.12 GMADR - Graphics Memory Range Address

      112
    • 1.9.13 GTTADR - Graphics Translation Table Range Address

      113
    • 1.9.14 SVID2 - Subsystem Vendor Identification

      113
    • 1.9.15 SID2 - Subsystem Identification

      114
    • 1.9.16 ROMADR - Video BIOS ROM Base Address

      114
    • 1.9.17 CAPPOINT - Capabilities Pointer

      115
    • 1.9.18 INTRLINE - Interrupt Line

      115
    • 1.9.19 INTRPIN - Interrupt Pin

      116
    • 1.9.20 MINGNT - Minimum Grant

      116
    • 1.9.21 MAXLAT - Maximum Latency

      116
    • 1.9.22 CAPID0 - Mirror of Device 0 Capability Identifier

      117
    • 1.9.23 MGGC - GMCH Graphics Control Register

      118
    • 1.9.24 DEVEN - Device Enable

      120
    • 1.9.25 SSRW - Software Scratch Read Write

      121
    • 1.9.26 BSM - Base of Stolen Memory

      121
    • 1.9.27 HSRW - Hardware Scratch Read Write

      122
    • 1.9.28 MSAC - Multi Size Aperture Control

      122
    • 1.9.29 SCWBFC - Secondary CWB Flush Control

      123
    • 1.9.30 MSI_CAPID - Message Signaled Interrupts Capability ID

      123
    • 1.9.31 MC - Message Control

      124
    • 1.9.32 MA - Message Address

      125
    • 1.9.33 MD - Message Data

      125
    • 1.9.34 GDRST - Graphics Debug Reset

      126
    • 1.9.35 PMCAPID - Power Management Capabilities ID

      127
    • 1.9.36 PMCAP - Power Management Capabilities

      127
    • 1.9.37 PMCS - Power Management Control/Status

      128
    • 1.9.38 SWSMI - Software SMI

      129
    • 1.9.39 LBB - LBB-Legacy Backlight Brightness

      130
  • 1.10 PCI Device 2 Function 1

    130
    • 1.10.1 VID2 - Vendor Identification

      132
    • 1.10.2 DID2 - Device Identification

      133
    • 1.10.3 PCICMD2 - PCI Command

      133
    • 1.10.4 PCISTS2 - PCI Status

      135
    • 1.10.5 RID2 - Revision Identification

      136
    • 1.10.6 CC - Class Code Register

      137
    • 1.10.7 CLS - Cache Line Size

      137
    • 1.10.8 MLT2 - Master Latency Timer

      138
    • 1.10.9 HDR2 - Header Type

      138
    • 1.10.10 MMADR - Memory Mapped Range Address

      139
    • 1.10.11 SVID2 - Subsystem Vendor Identification

      139
    • 1.10.12 SID2 - Subsystem Identification

      140
    • 1.10.13 ROMADR - Video BIOS ROM Base Address

      140
    • 1.10.14 CAPPOINT - Capabilities Pointer

      141
    • 1.10.15 MINGNT - Minimum Grant

      141
    • 1.10.16 MAXLAT - Maximum Latency

      141
    • 1.10.17 CAPID0 - Mirror of Device 0 Capability Identifier

      142
    • 1.10.18 MGGC - Mirror of Dev 0 GMCH Graphics Control Register

      143
    • 1.10.19 DEVEN - Device Enable

      145
    • 1.10.20 SSRW - Mirror of Fun 0 Software Scratch Read Write

      146
    • 1.10.21 BSM - Mirror of Func0 Base of Stolen Memory

      146
    • 1.10.22 HSRW - Mirror of Dev2 Func0 Hardware Scratch Read Write

      147
    • 1.10.23 MSAC - Mirror of Dev2 Func0 Multi Size Aperture Control

      147
    • 1.10.24 GDRST - Mirror of Dev2 Func0 Graphics Debug Reset

      148
    • 1.10.25 PMCAPID - Mirror of Fun 0 Power Management Capabilities ID

      149
    • 1.10.26 PMCAP - Mirror of Fun 0 Power Management Capabilities

      149
    • 1.10.27 PMCS - Power Management Control/Status

      150
    • 1.10.28 SWSMI - Mirror of Func0 Software SMI

      151
  • 1.11 Device 2 IO

    152
    • 1.11.1 Index - MMIO Address Register

      152
    • 1.11.2 Data - MMIO Data Register

      153