Intel D425 AU80610006252AA Manuel D’Utilisation

Datasheet 

 27 

Some of the CPU registers described in this section contain reserved bits. These bits 
are labeled "Reserved”. Software must deal correctly with fields that are reserved. On 

reads, software must use appropriate masks to extract the defined bits and not rely 
on reserved bits being any particular value. On writes, software must ensure that the 

values of reserved bit positions are preserved. That is, the values of reserved bit 

positions must first be read, merged with the new values for other bit positions and 
then written back. Note the software does not need to perform read, merge, write 

operation for the configuration address register. 

In addition to reserved bits within a register, CPU contains address locations in the 
configuration space of the Host Bridge entity that are marked either "Reserved" or 

“Intel Reserved”. The CPU responds to accesses to “Reserved” address locations by 
completing the host cycle. When a “Reserved” register location is read, a zero value is 

returned. (“Reserved” registers can be 8-, 16-, or 32-bit in size). Writes to “Reserved” 

registers have no effect on the CPU. Registers that are marked as “Intel Reserved” 
must not be modified by system software. Writes to “Intel Reserved” registers may 

cause system failure. Reads to “Intel Reserved” registers may return a non-zero 

value. 

Upon a Full Reset, CPU sets all of its internal configuration registers to predetermined 
default states. Some register values at reset are determined by external strapping 

options, or the states of poly-silicon fuses. The default state represents the minimum 

functionality feature set required to successfully bring up the system. Hence, it does 

not represent the optimal system configuration. It is the responsibility of the system 
initialization software (usually BIOS) to properly determine the DRAM configurations, 

operating parameters and optional system features that are applicable, and to 

program the CPU registers accordingly. 

The processor contains two registers that reside in the processor I/O address space − 
the Configuration Address (CONFIG_ADDRESS) Register and the Configuration Data 

(CONFIG_DATA) Register. The Configuration Address Register enables/disables the 

configuration space and determines what portion of configuration space is visible 
through the Configuration Data window.