Intel Xeon L3406 CM80616005010AA Manuel D’Utilisation
Codes de produits
CM80616005010AA
Datasheet, Volume 2
77
Processor Integrated I/O (IIO) Configuration Registers
3.3.4.33
PMCSR—Power Management Control and Status
Register (Device 0 DMI)
This register provides status and control information for PM events on the DMI port..
.
Register:
PMCSR
Device:
0 (DMI)
Function:
0
Offset:
E4h
Bit
Attr
Default
Description
31:24
RO
00h
Reserved
23
RO
0h
Bus Power/Clock Control Enable
This field is hardwired to 0h as it does not apply to PCI Express.
This field is hardwired to 0h as it does not apply to PCI Express.
22
RO
0h
B2/B3 Support
This field is hardwired to 0h as it does not apply to PCI Express.
This field is hardwired to 0h as it does not apply to PCI Express.
21:16
RV
0h
Reserved
15
RO
0h
Reserved
14:13
RO
0h
Reserved
12:9
RO
0h
Reserved
8
RO
0h
Reserved
7:4
RV
0h
Reserved
3
RV
0h
Reserved
2
RV
0h
Reserved
1:0
RO
0h
Power State
This 2-bit field is used to determine the current power state of the function
This 2-bit field is used to determine the current power state of the function
and to set a new power state.
00 = D0 (default)
01 = D1 (not supported by Integrated I/O)
10 = D2 (not supported by Integrated I/O)
11 = D3hot
If Software tries to write 01 or 10 to this field, the power state does not
00 = D0 (default)
01 = D1 (not supported by Integrated I/O)
10 = D2 (not supported by Integrated I/O)
11 = D3hot
If Software tries to write 01 or 10 to this field, the power state does not
change from the existing power state (which is either D0 or D3hot) and nor
do these bits change value.