Intel Xeon L3406 CM80616005010AA Manuel D’Utilisation
Codes de produits
CM80616005010AA
Processor Integrated I/O (IIO) Configuration Registers
78
Datasheet, Volume 2
3.3.4.34
PMCSR—Power Management Control and Status Register
This register provides status and control information for PM events in the PCI Express
ports of the Integrated I/O.
ports of the Integrated I/O.
Register:
PMCSR
Device: 3-6
(PCIe)
Function:
0
Offset:
E4h
Bit
Attr
Default
Description
31:24
RO
00h
Reserved
23
RO
0h
Bus Power/Clock Control Enable
This field is hardwired to 0h as it does not apply to PCI Express.
This field is hardwired to 0h as it does not apply to PCI Express.
22
RO
0h
Reserved
21:16
RV
0h
Reserved
15
RV
0h
Reserved
14:13
RO
0h
Reserved
12:9
RO
0h
Reserved
8
RWS
0h
Reserved
7:4
RV
0h
Reserved
3
RWO
1
Reserved
2
RV
0h
Reserved
1:0
RW
0h
Power State
This 2-bit field is used to determine the current power state of the
This 2-bit field is used to determine the current power state of the
function and to set a new power state.
00 = D0 (default)
01 = D1 (not supported by Integrated I/O)
10 = D2 (not supported by Integrated I/O)
11 = D3hot
If Software tries to write 01 or 10 to this field, the power state does not
00 = D0 (default)
01 = D1 (not supported by Integrated I/O)
10 = D2 (not supported by Integrated I/O)
11 = D3hot
If Software tries to write 01 or 10 to this field, the power state does not
change from the existing power state (which is either D0 or D3hot) and
nor do these bits change value.