Epson arm.powered arm720t Manuel D’Utilisation

A microprocessor that recognizes a large number of instructions.

See also 

Reduced Instruction Set Computer.

See 

Program Status Register.

The bottom eight bits of a program status register. The control bits change 

when an exception arises and can be altered by software only when the 

processor is in a privileged mode.

See 

Program Status Register.

Debug Communications Channel.

A condition that allows the monitoring and control of the execution of a 

processor. Usually used to find errors in the application program flow. A 

processor enters debug state from 

halt mode

 and not from 

monitor mode

. 

A debugging system which includes a program, used to detect, locate, and 

correct software faults, together with custom hardware that supports 

software debugging.

The EmbeddedICE logic is controlled via the JTAG test access port, using 

a protocol converter such as MultiICE: an extra piece of hardware that 

allows software tools to debug code running on a target processor. 

See also

 ICE and JTAG.

A version of EmbeddedICE logic that has improved support for real-time 

debugging.

Privileged modes that are entered when specific exceptions occur.

Handles an event. For example, an exception could handle an external 

interrupt or an undefined instruction.

An abort that is generated by the external memory system.

Fast interrupt.