Epson arm.powered arm720t Manuel D’Utilisation

One of two debugging modes. When debugging is performed in halt mode, 

the core stops when it encounters a watchpoint or breakpoint, and is 

isolated from the rest of the system. See also 

Monitor mode

.

See 

In-circuit emulator.

A mathematical quantity that when applied to itself under a given binary 

operation equals itself.

An 

In-Circuit Emulator

 (ICE), is a device that aids the debugging of 

hardware and software. Debuggable ARM processors such as the 

ARM720T processor have extra hardware to assist this process. 

See also 

EmbeddedICE-RT.

Interrupt request.

The name of the organization that developed standard IEEE 1149.1. This 

standard defines a boundary-scan architecture used for in-circuit testing of 

integrated circuit devices.

See 

Joint Test Action Group

.

This register holds the address of the next instruction after a branch with 

link instruction.

Memory organization where the most significant byte of a word is at a 

higher address than the least significant byte.

See 

Link register

A complex logic block with a defined interface and behavior. A typical VLSI 

system will comprise several macrocells (such as an ARM7TDMI-S core, an 

ETM7, and a memory block) plus application-specific logic.

Allows control of a memory system. Most of the control is provided through 

translation tables held in memory. 

See 

Memory Management Unit