NEC PD754244 Manuel D’Utilisation

User’s Manual  U10676EJ3V0UM

The input or output mode of each I/O port is set by the corresponding port mode register as shown in Figure 6-

10.  Ports 3 and 6 can be set to the input or output mode in 1-bit units by using port mode register group A (PMGA).

Port 8 is set to the input or output mode by using port mode register group C (PMGC).

Each port is set to the input mode when the corresponding port mode register bit is “0” and in the output mode

when the corresponding register bit is “1”.

When a port is set to the output mode by the corresponding port mode register, the contents of the output latch

are output to the output pin(s).  Before setting the output mode, therefore, the necessary value must be written to

the output latch.

Port mode register groups A and C are set by using an 8-bit memory manipulation instruction.

When the RESET signal is asserted, all the bits of each port mode register are cleared to 0, the output buffer is

turned off, and the corresponding port is set to the input mode.

To use P30, 31, 62, and 63 as input pins and P32, 33, 60, and 61 as output pins

CLR1

MBE

; or SEL MB15

MOV

XA, #3CH

MOV

PMGA, XA