Manuel D’UtilisationTable des matièresCOVER1Major Revisions in This Edition6INTRODUCTION7CHAPTER 1 GENERAL171.1 Functional Outline181.2 Ordering Information191.3 Differences Between Series Products191.4 Block Diagram201.5 Pin Configuration (Top View)21CHAPTER 2 PIN FUNCTIONS242.1 Pin Functions of uPD754244242.2 Description of Pin Functions262.2.1 P30 to P33 (Port 3), P60 to P63 (Port 6), P80 (Port 8)262.2.2 P70 to P73 (Port 7)262.2.3 PTO0 to PTO2262.2.4 INT0272.2.5 KR4 to KR7272.2.6 KRREN272.2.7 TH00 and TH01272.2.8 AVREF282.2.9 CL1 and CL2 (uPD754144 only)282.2.10 X1 and X2 (uPD754244 only)282.2.11 RESET#282.2.12 IC292.2.13 VDD292.2.14 VSS292.3 Pin I/O Circuits302.4 Processing of Unused Pins31CHAPTER 3 FEATURES OF ARCHITECTURE AND MEMORY MAP323.1 Bank Configuration of Data Memory and Addressing Modes323.1.1 Bank configuration of data memory323.1.2 Addressing mode of data memory343.2 Bank Configuration of General-Purpose Registers453.3 Memory-Mapped I/O50CHAPTER 4 INTERNAL CPU FUNCTION604.1 Function to Select MkI and MkII Modes604.1.1 Difference between MkI and MkII modes604.1.2 Setting stack bank select register (SBS)614.2 Program Counter (PC)624.3 Program Memory (ROM)634.4 Data Memory (RAM)654.4.1 Configuration of data memory654.4.2 Specifying bank of data memory664.5 General-Purpose Registers694.6 Accumulator704.7 Stack Pointer (SP) and Stack Bank Select Register (SBS)704.8 Program Status Word (PSW)744.9 Bank Select Register (BS)78CHAPTER 5 EEPROM805.1 EEPROM Configuration805.2 EEPROM Features805.3 EEPROM Write Control Register (EWC)815.4 Interrupt Related to EEPROM Control825.5 EEPROM Manipulation Method835.5.1 EEPROM manipulation instructions835.5.2 Read manipulation845.5.3 Write manipulation855.6 Cautions on EEPROM Writing87CHAPTER 6 PERIPHERAL HARDWARE FUNCTION886.1 Digital I/O Ports886.1.1 Types, features, and configurations of digital I/O ports896.1.2 Setting I/O mode946.1.3 Digital I/O port manipulation instruction966.1.4 Operation of digital I/O port986.1.5 Connecting pull-up resistor1006.1.6 I/O timing of digital I/O port1016.2 Clock Generator1036.2.1 Configuration of clock generator1036.2.2 Function and operation of clock generator1056.2.3 Setting CPU clock1126.3 Basic Interval Timer/Watchdog Timer1146.3.1 Configuration of basic interval timer/watchdog timer1146.3.2 Basic interval timer mode register (BTM)1156.3.3 Watchdog timer enable flag (WDTM)1176.3.4 Operation as basic interval timer1186.3.5 Operation as watchdog timer1196.3.6 Other functions1216.4 Timer Counter1226.4.1 Configuration of timer counter1226.4.2 Operation in 8-bit timer counter mode1346.4.3 Operation in PWM pulse generator mode (PWM mode)1456.4.4 Operation in 16-bit timer counter mode1516.4.5 Operation in carrier generator mode (CG mode)1606.4.6 Notes on using timer counter1736.5 Programmable Threshold Port (Analog Input Port)1806.5.1 Configuration and operation of programmable threshold port1806.5.2 Programmable threshold port mode (PTHM) register1826.5.3 Programmable threshold port application1836.6 Bit Sequential Buffer184CHAPTER 7 INTERRUPT AND TEST FUNCTIONS1867.1 Configuration of Interrupt Controller1867.2 Types of Interrupt Sources and Vector Table1887.3 Hardware Controlling Interrupt Function1907.4 Interrupt Sequence1977.5 Nesting Control of Interrupts1987.6 Servicing of Interrupts Sharing Vector Address2007.7 Machine Cycles Until Interrupt Servicing2027.8 Effective Usage of Interrupts2047.9 Application of Interrupt2047.10 Test Function2127.10.1 Types of test sources2127.10.2 Hardware controlling test function212CHAPTER 8 STANDBY FUNCTION2158.1 Settings and Operating Statuses of Standby Mode2168.2 Releasing Standby Mode2188.3 Operation After Release of Standby Mode2228.4 Application of Standby Mode222CHAPTER 9 RESET FUNCTION2279.1 Configuration and Operation of Reset Function2279.2 Watchdog Flag (WDF), Key Return Flag (KRF)231CHAPTER 10 MASK OPTIONS23310.1 Pin Mask Options23310.1.1 Mask option of P70/KR4 to P73/KR723310.1.2 RESET# pin mask option23310.2 Oscillation Stabilization Wait Time Mask Option233CHAPTER 11 INSTRUCTION SET23411.1 Unique Instructions23411.1.1 GETI instruction23411.1.2 Bit manipulation instruction23511.1.3 String-effect instruction23511.1.4 Base number adjustment instruction23611.1.5 Skip instruction and number of machine cycles required for skipping23711.2 Instruction Set and Operation23711.3 Opcode of Each Instruction24811.4 Instruction Function and Application25411.4.1 Transfer instructions25511.4.2 Table reference instructions26111.4.3 Bit transfer instructions26511.4.4 Operation instructions26611.4.5 Accumulator manipulation instructions27211.4.6 Increment/decrement instructions27311.4.7 Compare instructions27411.4.8 Carry flag manipulation instructions27511.4.9 Memory bit manipulation instructions27611.4.10 Branch instructions27911.4.11 Subroutine/stack control instructions28311.4.12 Interrupt control instructions28711.4.13 Input/output instructions28811.4.14 CPU control instruction28911.4.15 Special instructions290APPENDIX A DEVELOPMENT TOOLS293APPENDIX B ORDERING MASK ROM297APPENDIX C INSTRUCTION INDEX298C.1 Instruction Index (By Function)298C.2 Instruction Index (Alphabetical Order)301APPENDIX D HARDWARE INDEX304APPENDIX E REVISION HISTORY306Taille: 1,7 MoPages: 306Language: EnglishOuvrir le manuel
Manuel D’UtilisationTable des matièresCOVER1Major Revisions in This Edition6INTRODUCTION7CHAPTER 1 GENERAL171.1 Functional Outline181.2 Ordering Information191.3 Differences Between Series Products191.4 Block Diagram201.5 Pin Configuration (Top View)21CHAPTER 2 PIN FUNCTIONS242.1 Pin Functions of uPD754244242.2 Description of Pin Functions262.2.1 P30 to P33 (Port 3), P60 to P63 (Port 6), P80 (Port 8)262.2.2 P70 to P73 (Port 7)262.2.3 PTO0 to PTO2262.2.4 INT0272.2.5 KR4 to KR7272.2.6 KRREN272.2.7 TH00 and TH01272.2.8 AVREF282.2.9 CL1 and CL2 (uPD754144 only)282.2.10 X1 and X2 (uPD754244 only)282.2.11 RESET#282.2.12 IC292.2.13 VDD292.2.14 VSS292.3 Pin I/O Circuits302.4 Processing of Unused Pins31CHAPTER 3 FEATURES OF ARCHITECTURE AND MEMORY MAP323.1 Bank Configuration of Data Memory and Addressing Modes323.1.1 Bank configuration of data memory323.1.2 Addressing mode of data memory343.2 Bank Configuration of General-Purpose Registers453.3 Memory-Mapped I/O50CHAPTER 4 INTERNAL CPU FUNCTION604.1 Function to Select MkI and MkII Modes604.1.1 Difference between MkI and MkII modes604.1.2 Setting stack bank select register (SBS)614.2 Program Counter (PC)624.3 Program Memory (ROM)634.4 Data Memory (RAM)654.4.1 Configuration of data memory654.4.2 Specifying bank of data memory664.5 General-Purpose Registers694.6 Accumulator704.7 Stack Pointer (SP) and Stack Bank Select Register (SBS)704.8 Program Status Word (PSW)744.9 Bank Select Register (BS)78CHAPTER 5 EEPROM805.1 EEPROM Configuration805.2 EEPROM Features805.3 EEPROM Write Control Register (EWC)815.4 Interrupt Related to EEPROM Control825.5 EEPROM Manipulation Method835.5.1 EEPROM manipulation instructions835.5.2 Read manipulation845.5.3 Write manipulation855.6 Cautions on EEPROM Writing87CHAPTER 6 PERIPHERAL HARDWARE FUNCTION886.1 Digital I/O Ports886.1.1 Types, features, and configurations of digital I/O ports896.1.2 Setting I/O mode946.1.3 Digital I/O port manipulation instruction966.1.4 Operation of digital I/O port986.1.5 Connecting pull-up resistor1006.1.6 I/O timing of digital I/O port1016.2 Clock Generator1036.2.1 Configuration of clock generator1036.2.2 Function and operation of clock generator1056.2.3 Setting CPU clock1126.3 Basic Interval Timer/Watchdog Timer1146.3.1 Configuration of basic interval timer/watchdog timer1146.3.2 Basic interval timer mode register (BTM)1156.3.3 Watchdog timer enable flag (WDTM)1176.3.4 Operation as basic interval timer1186.3.5 Operation as watchdog timer1196.3.6 Other functions1216.4 Timer Counter1226.4.1 Configuration of timer counter1226.4.2 Operation in 8-bit timer counter mode1346.4.3 Operation in PWM pulse generator mode (PWM mode)1456.4.4 Operation in 16-bit timer counter mode1516.4.5 Operation in carrier generator mode (CG mode)1606.4.6 Notes on using timer counter1736.5 Programmable Threshold Port (Analog Input Port)1806.5.1 Configuration and operation of programmable threshold port1806.5.2 Programmable threshold port mode (PTHM) register1826.5.3 Programmable threshold port application1836.6 Bit Sequential Buffer184CHAPTER 7 INTERRUPT AND TEST FUNCTIONS1867.1 Configuration of Interrupt Controller1867.2 Types of Interrupt Sources and Vector Table1887.3 Hardware Controlling Interrupt Function1907.4 Interrupt Sequence1977.5 Nesting Control of Interrupts1987.6 Servicing of Interrupts Sharing Vector Address2007.7 Machine Cycles Until Interrupt Servicing2027.8 Effective Usage of Interrupts2047.9 Application of Interrupt2047.10 Test Function2127.10.1 Types of test sources2127.10.2 Hardware controlling test function212CHAPTER 8 STANDBY FUNCTION2158.1 Settings and Operating Statuses of Standby Mode2168.2 Releasing Standby Mode2188.3 Operation After Release of Standby Mode2228.4 Application of Standby Mode222CHAPTER 9 RESET FUNCTION2279.1 Configuration and Operation of Reset Function2279.2 Watchdog Flag (WDF), Key Return Flag (KRF)231CHAPTER 10 MASK OPTIONS23310.1 Pin Mask Options23310.1.1 Mask option of P70/KR4 to P73/KR723310.1.2 RESET# pin mask option23310.2 Oscillation Stabilization Wait Time Mask Option233CHAPTER 11 INSTRUCTION SET23411.1 Unique Instructions23411.1.1 GETI instruction23411.1.2 Bit manipulation instruction23511.1.3 String-effect instruction23511.1.4 Base number adjustment instruction23611.1.5 Skip instruction and number of machine cycles required for skipping23711.2 Instruction Set and Operation23711.3 Opcode of Each Instruction24811.4 Instruction Function and Application25411.4.1 Transfer instructions25511.4.2 Table reference instructions26111.4.3 Bit transfer instructions26511.4.4 Operation instructions26611.4.5 Accumulator manipulation instructions27211.4.6 Increment/decrement instructions27311.4.7 Compare instructions27411.4.8 Carry flag manipulation instructions27511.4.9 Memory bit manipulation instructions27611.4.10 Branch instructions27911.4.11 Subroutine/stack control instructions28311.4.12 Interrupt control instructions28711.4.13 Input/output instructions28811.4.14 CPU control instruction28911.4.15 Special instructions290APPENDIX A DEVELOPMENT TOOLS293APPENDIX B ORDERING MASK ROM297APPENDIX C INSTRUCTION INDEX298C.1 Instruction Index (By Function)298C.2 Instruction Index (Alphabetical Order)301APPENDIX D HARDWARE INDEX304APPENDIX E REVISION HISTORY306Taille: 1,7 MoPages: 306Language: EnglishOuvrir le manuel