Gemalto M2M GmbH PDS6 Manuel D’Utilisation
PDS6_HIO_v02.800
Confidential / Preliminary
2014-10-27
Cinterion
®
PDS6 Hardware Interface Overview
2.1 Application Interface
Page 15 of 35
2.1.7
I
2
C Interface
I
2
C is a serial, 8-bit oriented data transfer bus for bit rates up to 400kbps in Fast mode. It con-
sists of two lines, the serial data line I2CDAT and the serial clock line I2CCLK. The module acts
as a single master device, e.g. the clock I2CCLK is driven by the module. I2CDAT is a bi-direc-
tional line. Each device connected to the bus is software addressable by a unique 7-bit ad-
dress, and simple master/slave relationships exist at all times. The module operates as master-
transmitter or as master-receiver. The customer application transmits or receives data only on
request of the module.
as a single master device, e.g. the clock I2CCLK is driven by the module. I2CDAT is a bi-direc-
tional line. Each device connected to the bus is software addressable by a unique 7-bit ad-
dress, and simple master/slave relationships exist at all times. The module operates as master-
transmitter or as master-receiver. The customer application transmits or receives data only on
request of the module.
The I
2
C interface can be powered via the V180 line of PDS6. If connected to the V180 line,
the I
2
C interface will properly shut down when the module enters the Power Down mode.
Note: Good care should be taken when creating the PCB layout of the host application: The
traces of I2CCLK and I2CDAT should be equal in length and as short as possible.
traces of I2CCLK and I2CDAT should be equal in length and as short as possible.
2.1.8
SPI Interface
The Serial Peripheral Interface (SPI) is a synchronous serial interface for control and data
transfer between PDS6 and the external application. Only one application can be connected
to the SPI and the interface supports only master mode. The transmission rates are up to
6.5Mbit/s. The SPI interface comprises the two data lines MOSI and MISO, the clock line
SPI_CLK a well as the chip select line SPI_CS.
transfer between PDS6 and the external application. Only one application can be connected
to the SPI and the interface supports only master mode. The transmission rates are up to
6.5Mbit/s. The SPI interface comprises the two data lines MOSI and MISO, the clock line
SPI_CLK a well as the chip select line SPI_CS.