Fujifilm Xeon DP S26361-F3310-L280 Fiche De Données
![Fujifilm](https://files.manualsbrain.com/attachments/92165c0a413be2bbfd4eb5f3c1cf768a66ca5e1e/common/fit/150/50/1c1990aa4fd68d6b9f8197ae2933df14f0e6eb9f522c7305b7540487c75a/brand_logo.png)
Codes de produits
S26361-F3310-L280
18
Datasheet
2.5
Reserved or Unused Pins
All Reserved pins must remain unconnected. Connection of these pins to V
CC
, V
TT
, V
SS
, or to any
other signal (including each other) can result in component malfunction or incompatibility with
future processors. See
future processors. See
for a pin listing of the processor and the location of all Reserved
pins.
For reliable operation, always connect unused inputs or bidirectional signals to an appropriate
signal level. In a system level design, on-die termination has been included by the processor to
allow end agents to be terminated within the processor silicon for most signals. In this context, end
agent refers to the bus agent that resides on either end of the daisy-chained front side bus interface
while a middle agent is any bus agent in between the two end agents. For end agents, most unused
AGTL+ inputs should be left as no connects as AGTL+ termination is provided on the processor
silicon. However, see
signal level. In a system level design, on-die termination has been included by the processor to
allow end agents to be terminated within the processor silicon for most signals. In this context, end
agent refers to the bus agent that resides on either end of the daisy-chained front side bus interface
while a middle agent is any bus agent in between the two end agents. For end agents, most unused
AGTL+ inputs should be left as no connects as AGTL+ termination is provided on the processor
silicon. However, see
for details on AGTL+ signals that do not include on-die termination.
For middle agents, the on-die termination must be disabled, so the platform must ensure that
unused AGTL+ input signals which do not connect to end agents are connected to V
unused AGTL+ input signals which do not connect to end agents are connected to V
TT
via a pull-
up resistor. Unused active high inputs, should be connected through a resistor to ground (V
SS
).
Unused outputs can be left unconnected, however this may interfere with some TAP functions,
complicate debug probing, and prevent boundary scan testing. A resistor must be used when tying
bidirectional signals to power or ground. When tying any signal to power or ground, a resistor will
also allow for system testability. Resistor values should be within ± 20% of the impedance of the
baseboard trace for front side bus signals. For unused AGTL+ input or I/O signals, use pull-up
resistors of the same value as the on-die termination resistors (R
complicate debug probing, and prevent boundary scan testing. A resistor must be used when tying
bidirectional signals to power or ground. When tying any signal to power or ground, a resistor will
also allow for system testability. Resistor values should be within ± 20% of the impedance of the
baseboard trace for front side bus signals. For unused AGTL+ input or I/O signals, use pull-up
resistors of the same value as the on-die termination resistors (R
TT
).
TAP, Asynchronous GTL+ inputs, and Asynchronous GTL+ outputs do not include on-die
termination. Inputs and utilized outputs must be terminated on the baseboard. Unused outputs may
be terminated on the baseboard or left unconnected. Note that leaving unused outputs unterminated
may interfere with some TAP functions, complicate debug probing, and prevent boundary scan
testing. Signal termination for these signal types is discussed in the ITP700 Debug Port Design
Guide (See
termination. Inputs and utilized outputs must be terminated on the baseboard. Unused outputs may
be terminated on the baseboard or left unconnected. Note that leaving unused outputs unterminated
may interfere with some TAP functions, complicate debug probing, and prevent boundary scan
testing. Signal termination for these signal types is discussed in the ITP700 Debug Port Design
Guide (See
All TESTHI[6:0] pins should be individually connected to V
TT
via a pull-up resistor which
matches the nominal trace impedance. TESTHI[3:0] and TESTHI[6:5] may be tied together and
pulled up to V
pulled up to V
TT
with a single resistor if desired. However, usage of boundary scan test will not be
functional if these pins are connected together. TESTHI4 must always be pulled up independently
from the other TESTHI pins. For optimum noise margin, all pull-up resistor values used for
TESTHI[6:0] pins should have a resistance value within ± 20% of the impedance of the board
transmission line traces. For example, if the nominal trace impedance is 50
from the other TESTHI pins. For optimum noise margin, all pull-up resistor values used for
TESTHI[6:0] pins should have a resistance value within ± 20% of the impedance of the board
transmission line traces. For example, if the nominal trace impedance is 50
Ω, then a value between
40
Ω and 60 Ω should be used.
N/C (no connect) pins of the processor are not used by the processor. There is no connection from
the pin to the die. These pins may perform functions in future processors intended for platforms
using the Low Voltage Intel
the pin to the die. These pins may perform functions in future processors intended for platforms
using the Low Voltage Intel
®
Xeon™ processor with 800 MHz system bus.