ECS K8M800-M2 K8M800-M2 (V2.0) Manuel D’Utilisation
Codes de produits
K8M800-M2 (V2.0)
36
Using BIOS
VLink Data Rate (8X)
This option allows you to select the data transfer rate between the Northbridge and
Southbridge chipsets.
Southbridge chipsets.
Init Display First (PCI slot)
Use this item to specify whether your graphics adapter is installed in one of the PCI
slots or is integrated on the motherboard.
slots or is integrated on the motherboard.
System BIOS Cacheable (Disabled)
This item allows the system to be cached in memory for faster execution. Enable this item
for better performance.
for better performance.
PCI1/2 Post Write (Enabled)
When enabled, writes from the CPU to PCU bus are buffered, to compensate for the
speeddifferences between the CPU and PCI bus. When disabled, the writes are not buffered and
theCPU must wait until the write is complete before starting another write cycle.
speeddifferences between the CPU and PCI bus. When disabled, the writes are not buffered and
theCPU must wait until the write is complete before starting another write cycle.
PCI Delay Transaction (Disabled)
The motherboard’s chipset has an embedded 32-bit post write buffer to support delay transactions
cycles. Select Enabled to support compliance with PCI specification version 2.1.
cycles. Select Enabled to support compliance with PCI specification version 2.1.
Press <Esc> to return to the Advanced Chipset Features page.
Integrated Peripherals
These options display items that define the operation of peripheral components on
the system’s input/output ports.
the system’s input/output ports.
VIA OnChip IDE Device
[Press Enter]
VIA OnChip PCI Device
[Press Enter]
SuperIO Device
[Press Enter]
Item Help
Menu Level
Phoenix-AwardBIOS CMOS Setup Utility
Integrated Peripherals
F5:Previous Values F6:Fail-Safe Defaults F7:Optimized Defaults
: Move Enter: Select +/-/PU/PD:Value F10:Save ESC:Exit F1: General Help