Texas Instruments Delfino C28346 DIM168 ControlCARD TMDSCNCD28346-168 TMDSCNCD28346-168 Fiche De Données
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TMDSCNCD28346-168
C4
C3
XCLKOUT
(B)
XCLKIN
(A)
C5
C9
C10
C1
C8
C6
SPRS516D – MARCH 2009 – REVISED AUGUST 2012
6.8
Clock Requirements and Characteristics
Table 6-6. XCLKIN/X1 Timing Requirements – PLL Enabled
NO.
MIN
MAX
UNIT
C9
t
f(CI)
Fall time, XCLKIN
(1)
4
ns
C10
t
r(CI)
Rise time, XCLKIN
(1)
4
ns
C11
t
w(CIL)
Pulse duration, XCLKIN low as a percentage of t
c(OSCCLK)
(1)
40
60
%
C12
t
w(CIH)
Pulse duration, XCLKIN high as a percentage of t
c(OSCCLK)
(1)
40
60
%
(1)
This applies to the X1 pin also.
Table 6-7. XCLKIN/X1 Timing Requirements – PLL Disabled
NO.
MIN
MAX
UNIT
C9
t
f(CI)
Fall time, XCLKIN
(1)
2
ns
C10
t
r(CI)
Rise time, XCLKIN
(1)
2
ns
C11
t
w(CIL)
Pulse duration, XCLKIN low as a percentage of t
c(OSCCLK)
(1)
45
55
%
C12
t
w(CIH)
Pulse duration, XCLKIN high as a percentage of t
c(OSCCLK)
(1)
45
55
%
(1)
This applies to the X1 pin also.
The possible configuration modes are shown in
Table 6-8. XCLKOUT Switching Characteristics (PLL Bypassed or Enabled)
(1) (2)
NO.
PARAMETER
MIN
TYP
MAX
UNIT
C1
t
c(XCO)
Cycle time, XCLKOUT
13.3
ns
C3
t
f(XCO)
Fall time, XCLKOUT
2
ns
C4
t
r(XCO)
Rise time, XCLKOUT
2
ns
C5
t
w(XCOL)
Pulse duration, XCLKOUT low
H – 2
H + 2
ns
C6
t
w(XCOH)
Pulse duration, XCLKOUT high
H – 2
H + 2
ns
t
p
PLL lock time
2600 t
c(OSCCLK)
(3)
cycles
(1)
A load of 40 pF is assumed for these parameters.
(2)
H = 0.5t
c(XCO)
(3)
OSCCLK is either the output of the on-chip oscillator or the output from an external oscillator.
A.
The relationship of XCLKIN to XCLKOUT depends on the divide factor chosen. The waveform relationship shown is
intended to illustrate the timing parameters only and may differ based on actual configuration.
intended to illustrate the timing parameters only and may differ based on actual configuration.
B.
XCLKOUT configured to reflect SYSCLKOUT.
Figure 6-4. Clock Timing
Copyright © 2009–2012, Texas Instruments Incorporated
Electrical Specifications
117
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