STMicroelectronics M24C64-WBN6P Memory IC M24C64-WBN6P Fiche De Données
Codes de produits
M24C64-WBN6P
DocID16891 Rev 28
M24C64-W M24C64-R M24C64-F
41
4.5 Device
addressing
To start communication between the bus master and the slave device, the bus master must
initiate a Start condition. Following this, the bus master sends the device select code, shown
in
initiate a Start condition. Following this, the bus master sends the device select code, shown
in
(on Serial Data (SDA), most significant bit first).
When the device select code is received, the device only responds if the Chip Enable
address is the same as the value on its Chip Enable E2,E1,E0 inputs.
address is the same as the value on its Chip Enable E2,E1,E0 inputs.
The 8
th
bit is the Read/Write bit (RW). This bit is set to 1 for Read and 0 for Write operations.
If a match occurs on the device select code, the corresponding device gives an
acknowledgment on Serial Data (SDA) during the 9
acknowledgment on Serial Data (SDA) during the 9
th
bit time. If the device does not match
the device select code, the device deselects itself from the bus, and goes into Standby
mode.
mode.
Table 2. Device select code
Device type identifier
(1)
1. The most significant bit, b7, is sent first.
Chip Enable address
(2)
2. E0, E1 and E2 are compared with the value read on input pins E0, E1,and E2.
RW
b7
b6
b5
b4
b3
b2
b1
b0
Device select code
when addressing the
memory array
when addressing the
memory array
1
0
1
0
E2
E1
E0
RW
Device select code
when accessing the
Identification page
when accessing the
Identification page
1
0
1
1
E2
E1
E0
RW