Microchip Technology Microstick for the 5V PIC24F K-series DM240013-2 DM240013-2 Fiche De Données
Codes de produits
DM240013-2
2013 Microchip Technology Inc.
DS30003030B-page 137
PIC24FV16KM204 FAMILY
11.0
I/O PORTS
All of the device pins (except V
DD
and V
SS
) are shared
between the peripherals and the parallel I/O ports. All
I/O input ports feature Schmitt Trigger inputs for
improved noise immunity.
I/O input ports feature Schmitt Trigger inputs for
improved noise immunity.
11.1
Parallel I/O (PIO) Ports
A Parallel I/O port that shares a pin with a peripheral is,
in general, subservient to the peripheral. The peripheral’s
output buffer data and control signals are provided to a
pair of multiplexers. The multiplexers select whether the
peripheral or the associated port has ownership of the
output data and control signals of the I/O pin. The logic
also prevents “loop through”, in which a port’s digital
output can drive the input of a peripheral that shares the
same pin.
in general, subservient to the peripheral. The peripheral’s
output buffer data and control signals are provided to a
pair of multiplexers. The multiplexers select whether the
peripheral or the associated port has ownership of the
output data and control signals of the I/O pin. The logic
also prevents “loop through”, in which a port’s digital
output can drive the input of a peripheral that shares the
same pin.
illustrates how ports are shared
with other peripherals and the associated I/O pin to which
they are connected.
they are connected.
When a peripheral is enabled and the peripheral is
actively driving an associated pin, the use of the pin as
a general purpose output pin is disabled. The I/O pin
may be read, but the output driver for the parallel port
bit will be disabled. If a peripheral is enabled, but the
peripheral is not actively driving a pin, that pin may be
driven by a port.
All port pins have three registers directly associated
with their operation as digital I/O. The Data Direction
register (TRISx) determines whether the pin is an input
or an output. If the Data Direction register bit is a ‘1’,
then the pin is an input. All port pins are defined as
inputs after a Reset. Reads from the Data Latch regis-
ter (LATx), read the latch. Writes to the latch, write the
latch. Reads from the port (PORTx), read the port pins;
writes to the port pins, write the latch.
Any bit and its associated data and control registers
that are not valid for a particular device will be
disabled. That means the corresponding LATx and
TRISx registers, and the port pin will read as zeros.
When a pin is shared with another peripheral or
function that is defined as an input only, it is
nevertheless regarded as a dedicated port because
there is no other competing source of outputs.
actively driving an associated pin, the use of the pin as
a general purpose output pin is disabled. The I/O pin
may be read, but the output driver for the parallel port
bit will be disabled. If a peripheral is enabled, but the
peripheral is not actively driving a pin, that pin may be
driven by a port.
All port pins have three registers directly associated
with their operation as digital I/O. The Data Direction
register (TRISx) determines whether the pin is an input
or an output. If the Data Direction register bit is a ‘1’,
then the pin is an input. All port pins are defined as
inputs after a Reset. Reads from the Data Latch regis-
ter (LATx), read the latch. Writes to the latch, write the
latch. Reads from the port (PORTx), read the port pins;
writes to the port pins, write the latch.
Any bit and its associated data and control registers
that are not valid for a particular device will be
disabled. That means the corresponding LATx and
TRISx registers, and the port pin will read as zeros.
When a pin is shared with another peripheral or
function that is defined as an input only, it is
nevertheless regarded as a dedicated port because
there is no other competing source of outputs.
FIGURE 11-1:
BLOCK DIAGRAM OF A TYPICAL SHARED PORT STRUCTURE
Note:
This data sheet summarizes the features of
this group of PIC24F devices. It is not
intended to be a comprehensive reference
source. For more information on the I/O
ports, refer to the “PIC24F Family
Reference Manual”
this group of PIC24F devices. It is not
intended to be a comprehensive reference
source. For more information on the I/O
ports, refer to the “PIC24F Family
Reference Manual”
, “I/O Ports with
Peripheral Pin Select (PPS)”
(DS39711).
Note that the PIC24FV16KM204 family
devices do not support Peripheral Pin
Select features.
devices do not support Peripheral Pin
Select features.
Q
D
CK
WR LAT +
TRIS Latch
I/O Pin
WR PORT
Data Bus
Q
D
CK
Data Latch
Read PORT
Read TRIS
1
0
1
0
WR TRIS
Peripheral Output Data
Peripheral Input Data
I/O
Peripheral Module
Peripheral Output Enable
PIO Module
Output Multiplexers
Output Data
Input Data
Peripheral Module Enable
Read LAT
Output Enable