Fiche De Données (DM240013-2)Table des matièresAnalog Peripheral Features1High-Performance RISC CPU1Multiple/Single Capture Compare Peripheral (MCCP/SCCP) Features1Peripheral Features3Special Microcontroller Features3Pin Diagrams4Pin Diagrams (Continued)5Pin Diagrams (Continued)6Pin Diagrams (Continued)7Pin Diagrams (Continued)8Pin Diagrams (Continued)9Table of Contents10Most Current Data Sheet11Errata11Customer Notification System111.0 Device Overview131.1 Core Features131.1.1 16-Bit Architecture131.1.2 Power-saving Technology131.1.3 OSCILLATOR OPTIONS AND FEATURES131.1.4 EASY MIGRATION141.2 Other Special Features141.3 Details on Individual Family Members14TABLE 1-1: Device Features for the PIC24F16KM204 Family15TABLE 1-2: Device Features for the PIC24F16KM104 Family16TABLE 1-3: Device Features for the PIC24FV16KM204 Family17TABLE 1-4: Device Features for the PIC24FV16KM104 Family18FIGURE 1-1: PIC24FXXXXX Family General Block Diagrams19TABLE 1-5: PIC24FV16KM204 Family Pinout Description202.0 Guidelines for Getting Started with 16-Bit Microcontrollers292.1 Basic Connection Requirements29FIGURE 2-1: Recommended Minimum connections292.2 Power Supply Pins302.2.1 Decoupling Capacitors302.2.2 Tank Capacitors302.3 Master Clear (MCLR) Pin30FIGURE 2-2: Example of MCLR Pin Connections302.4 Voltage Regulator Pin (Vcap)31FIGURE 2-3: Frequency vs. ESR Performance for Suggested Vcap31TABLE 2-1: Suitable Capacitor Equivalents312.4.1 Considerations for Ceramic Capacitors32FIGURE 2-4: DC Bias Voltage vs. Capacitance Characteristics322.5 ICSP Pins322.6 External Oscillator Pins332.7 Unused I/Os33FIGURE 2-5: Suggested Placement of the Oscillator Circuit333.0 CPU353.1 Programmer’s Model35FIGURE 3-1: PIC24F CPU Core Block Diagram36TABLE 3-1: CPU Core Registers36FIGURE 3-2: Programmer’s Model373.2 CPU Control Registers38Register 3-1: SR: ALU STATUS Register38Register 3-2: CORCON: CPU Control Register393.3 Arithmetic Logic Unit (ALU)393.3.1 Multiplier393.3.2 Divider403.3.3 Multi-Bit Shift Support40TABLE 3-2: Instructions that Use the Single and Multi-Bit Shift Operation404.0 Memory Organization414.1 Program Address Space41FIGURE 4-1: Program Space Memory Map for PIC24FXXXXX Family Devices414.1.1 Program Memory Organization424.1.2 Hard Memory Vectors424.1.3 Data EEPROM424.1.4 Device Configuration Words42TABLE 4-1: Device Configuration Words for PIC24FXXXXX Family Devices42FIGURE 4-2: Program Memory Organization424.2 Data Address Space434.2.1 Data Space Width43FIGURE 4-3: Data Space Memory Map for PIC24FXXXXX Family Devices(3)434.2.2 Data Memory Organization and Alignment444.2.3 Near Data Space444.2.4 SFR Space44TABLE 4-2: Implemented Regions of SFR Data Space44TABLE 4-3: CPU CORE Registers Map45TABLE 4-4: ICN Register Map46TABLE 4-5: Interrupt Controller Register Map47TABLE 4-6: Timer1 Register Map48TABLE 4-7: CLC1-2 Register Map48TABLE 4-8: MCCP1 Register Map49TABLE 4-9: MCCP2 Register Map50TABLE 4-10: MCCP3 Register Map51TABLE 4-11: SCCP4 Register Map52TABLE 4-12: SCCP5 Register Map53TABLE 4-13: MSSP1 (I2C™/SPI) Register Map54TABLE 4-14: MSSP2 (I2C™/SPI) Register Map54TABLE 4-15: UART1 Register Map55TABLE 4-16: UART2 Register Map55TABLE 4-17: OP AMP 1 Register Map56TABLE 4-18: OP AMP 2 Register Map56TABLE 4-19: DAC1 Register Map56TABLE 4-20: DAC2 Register Map56TABLE 4-21: PORTA Register Map57TABLE 4-22: PORTb Register Map57TABLE 4-23: PORTC Register Map57TABLE 4-24: Pad Configuration Register Map58TABLE 4-25: A/D Register Map59TABLE 4-26: CTMU Register Map60TABLE 4-27: ANSEL Register Map60TABLE 4-28: Real-Time Clock and Calendar Register Map60TABLE 4-29: Comparator Register Map61TABLE 4-30: Band gap Buffer Control Register Map61TABLE 4-31: Clock Control Register Map62TABLE 4-32: NVM Register Map62TABLE 4-33: Ultra Low-Power Wake-up Register Map62TABLE 4-34: PMD Register Map624.2.5 Software Stack63FIGURE 4-4: CALL Stack Frame634.3 Interfacing Program and Data Memory Spaces634.3.1 Addressing Program Space63TABLE 4-35: Program Space Address Construction64FIGURE 4-5: Data Access From Program Space Address Generation644.3.2 Data Access From Program Memory and Data EEPROM Memory Using Table Instructions65FIGURE 4-6: Accessing Program Memory with Table Instructions654.3.3 Reading Data From Program Memory Using Program Space Visibility66FIGURE 4-7: Program Space Visibility Operation665.0 Flash Program Memory675.1 Table Instructions and Flash Programming67FIGURE 5-1: Addressing for Table Registers675.2 RTSP Operation685.3 Enhanced In-Circuit Serial Programming685.4 Control Registers685.5 Programming Operations68Register 5-1: NVMCON: Flash Memory Control Register695.5.1 Programming Algorithm for Flash Program Memory70EXAMPLE 5-1: Erasing a Program Memory Row – Assembly Language Code70EXAMPLE 5-2: Erasing a Program Memory Row – ‘C’ Language Code70EXAMPLE 5-3: Loading the Write Buffers – Assembly Language Code71EXAMPLE 5-4: Loading the Write Buffers – ‘C’ Language Code71EXAMPLE 5-5: Initiating a Programming Sequence – Assembly Language Code72EXAMPLE 5-6: Initiating a Programming Sequence – ‘C’ Language Code726.0 Data EEPROM Memory736.1 NVMCON Register736.2 NVMKEY Register73EXAMPLE 6-1: Data EEPROM Unlock Sequence73Register 6-1: NVMCON: Nonvolatile Memory Control Register746.3 NVM Address Register75FIGURE 6-1: Data EEPROM Addressing with TBLPAG and NVM Address Registers756.4 Data EEPROM Operations756.4.1 Erase Data EEPROM76EXAMPLE 6-2: Single-Word Erase766.4.2 Single-Word Write77EXAMPLE 6-3: Data EEPROM Bulk Erase77EXAMPLE 6-4: Single-Word Write to Data EEPROM776.4.3 Reading the Data EEPROM78EXAMPLE 6-5: Reading the Data EEPROM Using the TBLRD Command787.0 Resets79FIGURE 7-1: Reset System Block Diagram79Register 7-1: RCON: Reset Control Register(1)80TABLE 7-1: Reset Flag Bit Operation817.1 Clock Source Selection at Reset82TABLE 7-2: Oscillator Selection vs. Type of Reset (Clock Switching Enabled)827.2 Device Reset Times82TABLE 7-3: Reset Delay Times for Various Device Resets827.2.1 POR and Long Oscillator Start-up Times837.2.2 Fail-Safe Clock Monitor (FSCM) and Device Resets837.3 Special Function Register Reset States837.4 Brown-out Reset (BOR)837.4.1 Low-Power BOR (LPBOR)837.4.2 Software Enabled BOR847.4.3 Detecting BOR847.4.4 Disabling BOR in Sleep Mode848.0 Interrupt Controller858.1 Interrupt Vector Table (IVT)858.1.1 Alternate Interrupt Vector Table (AIVT)858.2 Reset Sequence85FIGURE 8-1: PIC24F Interrupt Vector Table86TABLE 8-1: Trap Vector Details87TABLE 8-2: Implemented Interrupt Vectors878.3 Interrupt Control and Status Registers88Register 8-1: SR: ALU STATUS Register89Register 8-2: CORCON: CPU Control Register90Register 8-3: INTCON1: Interrupt Control Register 191Register 8-4: INTCON2: Interrupt Control Register 292Register 8-5: IFS0: Interrupt Flag Status Register 093Register 8-6: IFS1: Interrupt Flag Status Register 194Register 8-7: IFS2: Interrupt Flag Status Register 295Register 8-8: IFS3: Interrupt Flag Status Register 395Register 8-9: IFS4: Interrupt Flag Status Register 496Register 8-10: IFS5: Interrupt Flag Status Register 597Register 8-11: IFS6: Interrupt Flag Status Register 697Register 8-12: IEC0: Interrupt Enable Control Register 098Register 8-13: IEC1: Interrupt Enable Control Register 199Register 8-14: IEC2: Interrupt Enable Control Register 2100Register 8-15: IEC3: Interrupt Enable Control Register 3100Register 8-16: IEC4: Interrupt Enable Control Register 4101Register 8-17: Iec5: Interrupt ENABLE CONTROL Register 5102Register 8-18: Iec6: Interrupt ENABLE CONTROL Register 5102Register 8-19: IPC0: Interrupt Priority Control Register 0103Register 8-20: IPC1: Interrupt Priority Control Register 1104Register 8-21: IPC2: Interrupt Priority Control Register 2105Register 8-22: IPC3: Interrupt Priority Control Register 3106Register 8-23: IPC4: Interrupt Priority Control Register 4107Register 8-24: IPC5: Interrupt Priority Control Register 5108Register 8-25: IPC6: Interrupt Priority Control Register 6109Register 8-26: IPC7: Interrupt Priority Control Register 7110Register 8-27: IPC10: Interrupt Priority Control Register 10111Register 8-28: IPC12: Interrupt Priority Control Register 12112Register 8-29: IPC15: Interrupt Priority Control Register 15113Register 8-30: IPC16: Interrupt Priority Control Register 16114Register 8-31: IPC18: Interrupt Priority Control Register 18115Register 8-32: IPC19: Interrupt Priority Control Register 19116Register 8-33: IPC20: Interrupt Priority Control Register 20117Register 8-34: IPC24: Interrupt Priority Control Register 24117Register 8-35: INTTREG: Interrupt Control and Status Register1188.4 Interrupt Setup Procedures1198.4.1 Initialization1198.4.2 Interrupt Service Routine1198.4.3 Trap Service Routine (TSR)1198.4.4 Interrupt Disable1199.0 Oscillator Configuration121FIGURE 9-1: PIC24FXXXXX Family Clock Diagram1219.1 CPU Clocking Scheme1229.2 Initial Configuration on POR1229.2.1 Clock Switching Mode Configuration Bits122TABLE 9-1: Configuration Bit Values for Clock Selection1229.3 Control Registers123Register 9-1: OSCCON: Oscillator Control Register123Register 9-2: CLKDIV: Clock Divider Register125Register 9-3: OSCTUN: FRC OSCILLATOR TUNE REGISTER1269.4 Clock Switching Operation1279.4.1 Enabling Clock Switching1279.4.2 Oscillator Switching Sequence127EXAMPLE 9-1: Assembly Code Sequence For Clock Switching128EXAMPLE 9-2: Basic ‘C’ Code Sequence For Clock Switching1289.5 Reference Clock Output128Register 9-4: REFOCON: Reference Oscillator Control Register12910.0 Power-Saving Features13110.1 Clock Frequency and Clock Switching13110.2 Instruction-Based Power-Saving Modes13110.2.1 Sleep Mode131EXAMPLE 10-1: ‘C’ POWER-SAVING ENTRY13110.2.2 Idle Mode13210.2.3 Interrupts Coincident with Power Save Instructions13210.3 Ultra Low-Power Wake-up132EXAMPLE 10-2: ULTRA LOW-POWER WAKE-UP INITIALIZATION132FIGURE 10-1: Series Resistor132Register 10-1: ULPWCON: ULPWU Control Register13310.4 Voltage Regulator-Based Power-Saving Features13410.4.1 Run Mode13410.4.2 Sleep Mode13410.4.3 Retention Regulator13410.4.4 Retention Sleep Mode134TABLE 10-1: Voltage Regulation Configuration Settings for PIC24FXXXXX Family Devices13410.5 Doze Mode13510.6 Selective Peripheral Module Control13511.0 I/O Ports13711.1 Parallel I/O (PIO) Ports137FIGURE 11-1: Block Diagram of a Typical Shared Port Structure13711.1.1 Open-Drain Configuration13811.2 Configuring Analog Port Pins13811.2.1 ANALOG SELECTION REGISTER138Register 11-1: ANSA: PORTA Analog Selection Register138Register 11-2: ANSB: PORTB Analog Selection Register139Register 11-3: ANSC: PORTC Analog Selection Register13911.2.2 I/O Port Write/Read Timing14011.3 Input Change Notification (ICN)140EXAMPLE 11-1: Port Write/Read Example14012.0 Timer1141FIGURE 12-1: 16-Bit Timer1 Module Block Diagram141Register 12-1: T1CON: Timer1 Control Register14213.0 Capture/Compare/PWM/ Timer Modules (MCCP and SCCP)143FIGURE 13-1: MCCPx/SCCPx Conceptual Block Diagram14313.1 Time Base Generator144TABLE 13-1: Valid Timer Options for MCCPx/SCCPx Modes144FIGURE 13-2: Timer Clock generator14413.2 General Purpose Timer145TABLE 13-2: Timer Operation Mode14513.2.1 SYNC and Trigger Operation145FIGURE 13-3: Dual 16-Bit Timer Mode145FIGURE 13-4: 32-Bit Timer Mode14613.3 Output Compare Mode147TABLE 13-3: Output Compare/PWM Modes147FIGURE 13-5: Output Compare x Block Diagram14713.4 Input Capture Mode148TABLE 13-4: Input Capture Modes148FIGURE 13-6: Input Capture x Block Diagram14813.5 Auxiliary Output149TABLE 13-5: Auxiliary Output149Register 13-1: CCPxCON1L: CCPx Control 1 Low Registers150Register 13-2: CCPxCON1H: CCPx Control 1 High Registers152TABLE 13-6: Synchronization Sources153Register 13-3: CCPxCON2L: CCPx Control 2 Low Registers154TABLE 13-7: Auto-Shutdown and Gating Sources154Register 13-4: CCPxCON2H: CCPx Control 2 High Registers155Register 13-5: CCPxCON3L: CCPx Control 3 Low Registers (1)156Register 13-6: CCPxCON3H: CCPx Control 3 High Registers157Register 13-7: CCPxSTATL: CCPx STATUS Register15814.0 Master Synchronous Serial Port (MSSP)15914.1 I/O Pin Configuration for SPI159FIGURE 14-1: MSSPx Block Diagram (SPI Mode)160FIGURE 14-2: SPI Master/Slave Connection160FIGURE 14-3: MSSPx Block Diagram (I2C™ Mode)161FIGURE 14-4: MSSPx Block Diagram (I2C™ Master Mode)161Register 14-1: SSPxSTAT: MSSPx Status Register (SPI Mode)162Register 14-2: SSPxSTAT: MSSPx Status Register (I2C™ Mode)163Register 14-3: SSPxCON1: MSSPx Control Register 1 (SPI Mode)165Register 14-4: SSPxCON1: MSSPx Control Register 1 (I2C™ Mode)166Register 14-5: SSPxCON2: MSSPx Control Register 2 (I2C™ Mode)167Register 14-6: SSPxCON3: MSSPx Control Register 3 (SPI Mode)168Register 14-7: SSPxCON3: MSSPx Control Register 3 (I2C™ Mode)169Register 14-8: SSPxADD: MSSPx Slave Address/Baud Rate Generator Register170Register 14-9: SSPxMSK: I2C™ Slave Address Mask Register170Register 14-10: PADCFG1: Pad Configuration Control Register17115.0 Universal Asynchronous Receiver Transmitter (UART)173FIGURE 15-1: UARTx Module Simplified Block Diagram17315.1 UARTx Baud Rate Generator (BRG)174EQUATION 15-1: UARTx Baud Rate with BRGH = 0(1)174EQUATION 15-2: UARTx Baud Rate with BRGH = 1(1)174EXAMPLE 15-1: Baud Rate Error Calculation (BRGH = 0)(1)17415.2 Transmitting in 8-Bit Data Mode17515.3 Transmitting in 9-Bit Data Mode17515.4 Break and Sync Transmit Sequence17515.5 Receiving in 8-Bit or 9-Bit Data Mode17515.6 Operation of UxCTS and UxRTS Control Pins17515.7 Infrared Support17515.7.1 External IrDA Support – IrDA Clock Output17515.7.2 Built-in IrDA Encoder and Decoder175Register 15-1: UxMODE: UARTx Mode Register176Register 15-2: UxSTA: UARTx Status and Control Register178Register 15-3: UxTXREG: UARTx Transmit Register180Register 15-4: UxRXREG: UARTx Receive Register18016.0 Real-Time Clock and Calendar (RTCC)18116.1 RTCC Source Clock181FIGURE 16-1: RTCC Block Diagram18116.2 RTCC Module Registers18216.2.1 Register Mapping182TABLE 16-1: RTCVAL Register Mapping182TABLE 16-2: ALRMVAL Register Mapping18216.2.2 Write Lock18216.2.3 Selecting RTCC Clock Source182EXAMPLE 16-1: Setting the RTCWREN Bit in Assembly182EXAMPLE 16-2: Setting the RTCWREN Bit in ‘C’18216.2.4 RTCC Control Registers183Register 16-1: RCFGCAL: RTCC Calibration and Configuration Register(1)183Register 16-2: RTCPWC: RTCC Configuration Register 2(1)185Register 16-3: ALCFGRPT: Alarm Configuration Register18616.2.5 RTCVAL Register Mappings187Register 16-4: YEAR: Year Value Register(1)187Register 16-5: MTHDY: Month and Day Value Register(1)187Register 16-6: WKDYHR: Weekday and Hours Value Register(1)188Register 16-7: MINSEC: Minutes and Seconds Value Register18816.2.6 ALRMVAL Register Mappings189Register 16-8: ALMTHDY: Alarm Month and Day Value Register(1)189Register 16-9: ALWDHR: Alarm Weekday and Hours Value Register(1)189Register 16-10: ALMINSEC: Alarm Minutes and Seconds Value Register190Register 16-11: RTCCSWT: rtcc Control/Sample Window Timer Register(1)19116.3 Calibration192EQUATION 16-1:19216.4 Alarm19216.4.1 Configuring The Alarm19216.4.2 Alarm Interrupt192FIGURE 16-2: Alarm Mask Settings19316.5 Power Control19317.0 Configurable Logic Cell (CLC)195FIGURE 17-1: CLCx Module195FIGURE 17-2: CLCx Logic Function Combinatorial Options196FIGURE 17-3: CLCx Input Source Selection Diagram19717.1 Control Registers198Register 17-1: CLCxCONL: CLCx CONTROL REGISTER (LOW)198Register 17-2: CLCxCONH: CLCx Control REGISTER (HIGH)199Register 17-3: CLCxSEL: CLCx INPUT MUX SELECT REGISTER200Register 17-4: CLCxGLSL: CLCx GATE LOGIC INPUT SELECT LOW REGISTER202Register 17-5: CLCxGLSH: CLCx GATE LOGIC INPUT SELECT HIGH REGISTER20418.0 High/Low-Voltage Detect (HLVD)207FIGURE 18-1: High/Low-Voltage Detect (HLVD) Module Block Diagram207Register 18-1: HLVDCON: High/Low-Voltage Detect Control Register20819.0 12-Bit A/D Converter with Threshold Detect209FIGURE 19-1: 12-Bit A/D Converter Block Diagram21019.1 A/D Control Registers21219.1.1 Control Registers21219.1.2 A/D Result Buffers212Register 19-1: AD1CON1: A/DA/D Control Register 1213Register 19-2: AD1CON2: A/D Control Register 2215Register 19-3: AD1CON3: A/D Control Register 3216Register 19-4: AD1CON5: A/D Control Register 5217Register 19-5: AD1CHS: A/D Sample Select Register218Register 19-6: AD1CHITH: A/D Scan Compare Hit Register (High Word)(1)219Register 19-7: AD1CHITL: A/D Scan Compare Hit Register (Low Word)(1)220Register 19-8: AD1CSSH: A/D Input Scan Select Register (High Word)(1)221Register 19-9: AD1CSSL: A/D Input Scan Select Register (Low word)(1)221Register 19-10: AD1CTMENH: CTMU Enable Register (High Word)(1)222Register 19-11: AD1CTMENL: CTMU Enable Register (Low Word)(1)22219.2 A/D Sampling Requirements223EQUATION 19-1: A/D Conversion Clock Period223FIGURE 19-2: 12-Bit A/D Converter Analog Input Model22319.3 Transfer Function224FIGURE 19-3: 12-bit A/D Transfer Function22419.4 Buffer Data Formats225FIGURE 19-4: A/D Output Data Formats (12-Bit)225TABLE 19-1: Numerical Equivalents of Various Result Codes: 12-Bit Integer Formats225TABLE 19-2: Numerical Equivalents of Various Result Codes: 12-Bit Fractional Formats226FIGURE 19-5: A/D Output Data Formats (10-Bit)226TABLE 19-3: Numerical Equivalents of Various Result Codes: 10-Bit Integer Formats226TABLE 19-4: Numerical Equivalents of Various Result Codes: 10-Bit Fractional Formats22720.0 8-Bit Digital-to-Analog Converter (DAC)229FIGURE 20-1: Single DACx Simplified Block Diagram229Register 20-1: DACxCON: DACx Control Register230Register 20-2: BUFCON0: Internal Voltage reference Control Register 023221.0 Dual Operational Amplifier Module233FIGURE 21-1: Single operational Amplifier Block Diagram233Register 21-1: AMPxCON: OP AMP x Control Register(1)23422.0 Comparator Module235FIGURE 22-1: Comparator x Module Block Diagram235FIGURE 22-2: Individual Comparator Configurations236Register 22-1: CMxCON: Comparator x Control Registers237Register 22-2: CMSTAT: Comparator Module Status Register23823.0 Comparator Voltage Reference23923.1 Configuring the Comparator Voltage Reference239FIGURE 23-1: Comparator Voltage Reference Block Diagram239Register 23-1: CVRCON: Comparator Voltage Reference Control Register24024.0 Charge Time Measurement Unit (CTMU)24124.1 Measuring Capacitance241EQUATION 24-1:241FIGURE 24-1: Typical Connections and Internal Configuration for Capacitance Measurement24224.2 Measuring Time242FIGURE 24-2: Typical Connections and Internal Configuration for Time Measurement24224.3 Pulse Generation and Delay243FIGURE 24-3: Typical Connections and Internal Configuration for Pulse Delay Generation243Register 24-1: CTMUCON1L: CTMU Control 1 Low Register244Register 24-2: CTMUCON1H: CTMU Control 1 High Register246Register 24-3: CTMUCON2L: CTMU Control 2 Low Register24825.0 Special Features24925.1 Configuration Bits249TABLE 25-1: Configuration Registers Locations249Register 25-1: FBS: Boot Segment Configuration Register249Register 25-2: FGS: General Segment Configuration Register250Register 25-3: FoscSEL: Oscillator Selection Configuration Register250Register 25-4: Fosc: Oscillator Configuration Register251Register 25-5: FWDT: Watchdog Timer Configuration Register252Register 25-6: FPOR: Reset Configuration Register253Register 25-7: FICD: In-Circuit Debugger Configuration Register254Register 25-8: DEVID: Device ID Register255Register 25-9: DEVREV: Device Revision Register25625.2 On-Chip Voltage Regulator25725.2.1 Voltage Regulator Tracking Mode and Low-Voltage Detection257FIGURE 25-1: Connections for the On-Chip Voltage Regulator25725.2.2 Voltage Regulator Start-Up Time25725.3 Watchdog Timer (WDT)25725.3.1 Windowed Operation25825.3.2 Control Register258FIGURE 25-2: WDT Block Diagram25825.4 Program Verification and Code Protection25925.5 In-Circuit Serial Programming25925.6 In-Circuit Debugger25926.0 Development Support26126.1 MPLAB X Integrated Development Environment Software26126.2 MPLAB XC Compilers26226.3 MPASM Assembler26226.4 MPLINK Object Linker/ MPLIB Object Librarian26226.5 MPLAB Assembler, Linker and Librarian for Various Device Families26226.6 MPLAB X SIM Software Simulator26326.7 MPLAB REAL ICE In-Circuit Emulator System26326.8 MPLAB ICD 3 In-Circuit Debugger System26326.9 PICkit 3 In-Circuit Debugger/ Programmer26326.10 MPLAB PM3 Device Programmer26326.11 Demonstration/Development Boards, Evaluation Kits and Starter Kits26426.12 Third-Party Development Tools26427.0 Electrical Characteristics265Absolute Maximum Ratings(†)26527.1 DC Characteristics266FIGURE 27-1: PIC24FV16KM204 Family voltage-frequency graph (industrial)266FIGURE 27-2: PIC24F16KM204 Family voltage-frequency graph (industrial)266FIGURE 27-3: PIC24FV16KM204 Family voltage-frequency graph (Extended)267FIGURE 27-4: PIC24F16KM204 Family voltage-frequency graph (Extended)267TABLE 27-1: Thermal Operating Conditions268TABLE 27-2: Thermal Packaging Characteristics268TABLE 27-3: DC Characteristics: Temperature and Voltage Specifications268TABLE 27-4: High/Low-Voltage Detect Characteristics269TABLE 27-5: BOR Trip Points269TABLE 27-6: DC Characteristics: Operating Current (Idd)270TABLE 27-7: DC Characteristics: Idle Current (Iidle)271TABLE 27-8: DC Characteristics: Power-Down Current (Ipd)272TABLE 27-9: DC Characteristics: I/O Pin Input Specifications274TABLE 27-10: DC Characteristics: I/O Pin Output Specifications275TABLE 27-11: DC Characteristics: Program Memory275TABLE 27-12: DC Characteristics: Data EEPROM Memory276TABLE 27-13: DC Characteristics: Comparator276TABLE 27-14: DC Characteristics: Comparator Voltage Reference276TABLE 27-15: Internal Voltage Regulator Specifications277TABLE 27-16: CTMU Current Source Specifications277TABLE 27-17: Operational Amplifier Specifications27827.2 AC Characteristics and Timing Parameters279TABLE 27-18: Temperature and Voltage Specifications – AC279FIGURE 27-5: Load Conditions for Device Timing Specifications279TABLE 27-19: Capacitive Loading Requirements on Output Pins279FIGURE 27-6: External Clock Timing280TABLE 27-20: External Clock Timing Requirements280TABLE 27-21: PLL Clock Timing Specifications281TABLE 27-22: Internal RC Oscillator Accuracy281TABLE 27-23: Internal RC Oscillator Specifications281FIGURE 27-7: CLKO and I/O Timing Characteristics282TABLE 27-24: CLKO and I/O Timing Requirements282FIGURE 27-8: Reset, Watchdog Timer, Oscillator Start-up Timer and Power-up Timer Timing Characteristics283FIGURE 27-9: Brown-out Reset Characteristics284TABLE 27-25: Reset, Watchdog Timer, Oscillator Start-up Timer, Power-Up Timer and Brown-Out Reset Timing Requirements284TABLE 27-26: Comparator Timing Requirements285TABLE 27-27: Comparator Voltage Reference Settling Time Specifications285FIGURE 27-10: Capture/Compare/PWM Timings (MCCPx, SCCPx Modules)285TABLE 27-28: Capture/Compare/PWM Requirements (MCCPx, SCCPx Modules)285FIGURE 27-11: Example SPI Master Mode Timing (CKE = 0)286TABLE 27-29: Example SPI Mode Requirements (Master Mode, Cke = 0)286FIGURE 27-12: Example SPI Master Mode Timing (CKE = 1)287TABLE 27-30: Example SPI Mode Requirements (Master Mode, CKE = 1)287FIGURE 27-13: Example SPI Slave Mode Timing (CKE = 0)288TABLE 27-31: Example SPI Mode Requirements (Slave Mode Timing, CKE = 0)288FIGURE 27-14: Example SPI Slave Mode Timing (CKE = 1)289TABLE 27-32: Example SPI Slave Mode Requirements (CKE = 1)289FIGURE 27-15: I2C™ Bus Start/Stop Bits Timing290TABLE 27-33: I2C™ Bus Start/Stop Bits Requirements (Slave Mode)290FIGURE 27-16: I2C™ Bus Data Timing290TABLE 27-34: I2C™ Bus Data Requirements (Slave Mode)291FIGURE 27-17: MSSPx I2C™ Bus Start/Stop Bits Timing Waveforms292TABLE 27-35: I2C™ Bus Start/Stop Bits Requirements (Master Mode)292FIGURE 27-18: MSSPx I2C™ Bus Data Timing293TABLE 27-36: I2C™ Bus Data Requirements (Master Mode)293TABLE 27-37: A/D Module Specifications294FIGURE 27-19: A/D Conversion Timing295TABLE 27-38: A/D Conversion Timing Requirements(1)295TABLE 27-39: 8-Bit Digital-to-Analog Converter Specifications29628.0 Packaging Information29728.1 Package Marking Information29728.2 Package Details300Appendix A: Revision History325Revision A (February 2013)325Revision B (July 2013)325INDEX327The Microchip Web Site333Customer Change Notification Service333Customer Support333Product Identification System335Worldwide Sales and Service338Taille: 3,4 MoPages: 338Language: EnglishOuvrir le manuel