Microchip Technology TDGL019 Fiche De Données
PIC32MX1XX/2XX
DS60001168F-page 114
© 2011-2014 Microchip Technology Inc.
bit 4
CHDHIF:
Channel Destination Half Full Interrupt Flag bit
1
= Channel Destination Pointer has reached midpoint of destination (CHDPTR = CHDSIZ/2)
0
= No interrupt is pending
bit 3
CHBCIF:
Channel Block Transfer Complete Interrupt Flag bit
1
= A block transfer has been completed (the larger of CHSSIZ/CHDSIZ bytes has been transferred), or a
pattern match event occurs
0
= No interrupt is pending
bit 2
CHCCIF:
Channel Cell Transfer Complete Interrupt Flag bit
1
= A cell transfer has been completed (CHCSIZ bytes have been transferred)
0
= No interrupt is pending
bit 1
CHTAIF:
Channel Transfer Abort Interrupt Flag bit
1
= An interrupt matching CHAIRQ has been detected and the DMA transfer has been aborted
0
= No interrupt is pending
bit 0
CHERIF:
Channel Address Error Interrupt Flag bit
1
= A channel address error has been detected (either the source or the destination address is invalid)
0
= No interrupt is pending
REGISTER 9-9:
DCHxINT: DMA CHANNEL ‘x’ INTERRUPT CONTROL REGISTER (CONTINUED)