Microchip Technology MA160014 Fiche De Données
2010-2012 Microchip Technology Inc.
DS41412F-page 263
PIC18(L)F2X/4XK22
REGISTER 15-4:
SSPxCON3: SSPx CONTROL REGISTER 3
R-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
ACKTIM
PCIE
SCIE
BOEN
SDAHT
SBCDE
AHEN
DHEN
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
ACKTIM: Acknowledge Time Status bit (I
2
C mode only)
(3)
1
= Indicates the I
2
C bus is in an Acknowledge sequence, set on 8
th
falling edge of SCLx clock
0
= Not an Acknowledge sequence, cleared on 9
th
rising edge of SCLx clock
bit 6
PCIE: Stop Condition Interrupt Enable bit (I
2
C mode only)
1
= Enable interrupt on detection of Stop condition
0
= Stop detection interrupts are disabled
(2)
bit 5
SCIE: Start Condition Interrupt Enable bit (I
2
C mode only)
1
= Enable interrupt on detection of Start or Restart conditions
0
= Start detection interrupts are disabled
(2)
bit 4
BOEN: Buffer Overwrite Enable bit
In SPI Slave mode:
(1)
1
= SSPxBUF updates every time that a new data byte is shifted in ignoring the BF bit
0
= If new byte is received with BF bit of the SSPxSTAT register already set, SSPxOV bit of the
SSPxCON1 register is set, and the buffer is not updated
In I
2
C Master mode:
This bit is ignored.
In I
2
C Slave mode:
1
= SSPxBUF is updated and ACK is generated for a received address/data byte, ignoring the
state of the SSPxOV bit only if the BF bit = 0.
0
= SSPxBUF is only updated when SSPxOV is clear
bit 3
SDAHT: SDAx Hold Time Selection bit (I
2
C mode only)
1
= Minimum of 300 ns hold time on SDAx after the falling edge of SCLx
0
= Minimum of 100 ns hold time on SDAx after the falling edge of SCLx
bit 2
SBCDE: Slave Mode Bus Collision Detect Enable bit (I
2
C Slave mode only)
If on the rising edge of SCLx, SDAx is sampled low when the module is outputting a high state, the
BCLxIF bit of the PIR2 register is set, and bus goes idle
BCLxIF bit of the PIR2 register is set, and bus goes idle
1
= Enable slave bus collision interrupts
0
= Slave bus collision interrupts are disabled
bit 1
AHEN: Address Hold Enable bit (I
2
C Slave mode only)
1
= Following the 8th falling edge of SCLx for a matching received address byte; CKP bit of the
SSPxCON1 register will be cleared and the SCLx will be held low.
0
= Address holding is disabled
Note 1:
For daisy-chained SPI operation; allows the user to ignore all but the last received byte. SSPxOV is still
set when a new byte is received and BF = 1, but hardware continues to write the most recent byte to
SSPxBUF.
set when a new byte is received and BF = 1, but hardware continues to write the most recent byte to
SSPxBUF.
2:
This bit has no effect in Slave modes for which Start and Stop condition detection is explicitly listed as
enabled.
enabled.
3:
The ACKTIM Status bit is active only when the AHEN bit or DHEN bit is set.