Manuels d'utilisation pour Microchip Technology MA160014

Table des matières

• High-Performance RISC CPU:

  3
• Flexible Oscillator Structure:

  3
• Analog Features:

  3
• Extreme Low-Power Management PIC18(L)F2X/4XK22 with XLP:

  3
• Special Microcontroller Features:

  3
• Peripheral Highlights:

  3
• Pin Diagrams (28-pin)

  5
• Pin Diagrams (40-pin)

  6
• Pin Diagrams (44-pin)

  7
• Table of Contents

  11
• Most Current Data Sheet

  12
• Errata

  12
• Customer Notification System

  12
• 1.0 Device Overview

  13
  • 1.1 New Core Features

    13
    • 1.1.1 XLP Technology

      13
    • 1.1.2 Multiple Oscillator Options and Features

      13
  • 1.2 Other Special Features

    14
  • 1.3 Details on Individual Family Members

    14
    • TABLE 1-1: Device Features

      15
    • FIGURE 1-1: PIC18(L)F2X/4XK22 Family Block Diagram

      16
    • TABLE 1-2: PIC18(L)F2XK22 Pinout I/O Descriptions

      17
    • TABLE 1-3: PIC18(L)F4XK22 Pinout I/O Descriptions

      21
• 2.0 Oscillator Module (With Fail-Safe Clock Monitor)

  27
  • 2.1 Overview

    27
    • FIGURE 2-1: Simplified OSCILLATOR SYSTEM BLOCK DIAGRAM

      28
  • 2.2 Oscillator Control

    29
    • 2.2.1 Main System Clock Selection

      29
    • 2.2.2 Internal Frequency Selection

      29
    • 2.2.3 Low Frequency Selection

      29
    • 2.2.4 Power Management

      29
      • FIGURE 2-2: Internal Oscillator Mux Block Diagram

        30
      • FIGURE 2-3: PLL_Select Block Diagram

        30
      • TABLE 2-1: PLL_Select Truth Table

        30
      • FIGURE 2-4: Secondary Oscillator and External Clock Inputs

        31
  • 2.3 Register Definitions: Oscillator Control

    32
    • Register 2-1: OSCCON: Oscillator Control Register

      32
    • Register 2-2: OSCCON2: Oscillator Control Register 2

      33
  • 2.4 Clock Source Modes

    34
  • 2.5 External Clock Modes

    34
    • 2.5.1 Oscillator Start-up Timer (OST)

      34
      • TABLE 2-2: Oscillator Delay Examples

        34
    • 2.5.2 EC Mode

      34
      • FIGURE 2-5: External Clock (EC) Mode Operation

        34
    • 2.5.3 LP, XT, HS Modes

      35
      • FIGURE 2-6: Quartz Crystal Operation (LP, XT or HS Mode)

        35
      • FIGURE 2-7: Ceramic Resonator Operation (XT or HS Mode)

        35
    • 2.5.4 External RC Modes

      36
      • FIGURE 2-8: External RC Modes

        36
  • 2.6 Internal Clock Modes

    36
    • 2.6.1 INTOSC with I/O or Clockout

      36
  • 2.7 Register Definitions: Oscillator Tuning

    37
    • Register 2-3: OSCTUNE: Oscillator Tuning ReGister

      37
    • 2.7.1 LFINTOSC

      38
    • 2.7.2 Frequency Select Bits (IRCF)

      38
    • 2.7.3 INTOSC Frequency Drift

      38
  • 2.8 PLL Frequency Multiplier

    39
    • 2.8.1 PLL in External Oscillator Modes

      39
    • 2.8.2 PLL in HFINTOSC Modes

      39
  • 2.9 Effects of Power-Managed Modes on the Various Clock Sources

    40
  • 2.10 Power-up Delays

    40
    • TABLE 2-3: OSC1 and OSC2 Pin States in Sleep Mode

      41
  • 2.11 Clock Switching

    41
    • 2.11.1 System Clock Select (SCS<1:0>) Bits

      41
    • 2.11.2 Oscillator Start-up Time-out Status (OSTS) Bit

      41
    • 2.11.3 Clock Switch Timing

      42
  • 2.12 Two-Speed Clock Start-up Mode

    42
    • 2.12.1 Two-Speed Start-up Mode Configuration

      42
    • 2.12.2 Two-Speed Start-up Sequence

      43
    • 2.12.3 Checking Two-Speed Clock Status

      43
      • FIGURE 2-9: Clock Switch Timing

        43
  • 2.13 Fail-Safe Clock Monitor

    44
    • FIGURE 2-10: FSCM Block Diagram

      44
    • 2.13.1 Fail-Safe Detection

      44
    • 2.13.2 Fail-Safe Operation

      44
    • 2.13.3 Fail-Safe Condition Clearing

      44
    • 2.13.4 Reset or Wake-up from Sleep

      44
      • FIGURE 2-11: FSCM Timing Diagram

        45
      • TABLE 2-4: Registers Associated with Clock Sources

        45
      • TABLE 2-5: Configuration Registers Associated with Clock Sources

        45
• 3.0 Power-Managed Modes

  47
  • 3.1 Selecting Power-Managed Modes

    47
    • 3.1.1 Clock Sources

      47
    • 3.1.2 Entering Power-Managed Modes

      47
      • TABLE 3-1: Power-Managed Modes

        47
    • 3.1.3 Multiple Functions of the Sleep Command

      48
  • 3.2 Run Modes

    48
    • 3.2.1 PRI_RUN Mode

      48
    • 3.2.2 SEC_RUN Mode

      48
    • 3.2.3 RC_RUN Mode

      48
      • FIGURE 3-1: Transition Timing for Entry to SEC_RUN Mode

        49
      • FIGURE 3-2: Transition Timing From SEC_RUN Mode to PRI_RUN Mode (HSPLL)

        49
      • TABLE 3-2: Internal Oscillator Frequency Stability Bits

        50
      • FIGURE 3-3: Transition Timing From RC_RUN Mode to PRI_RUN Mode

        50
  • 3.3 Sleep Mode

    51
  • 3.4 Idle Modes

    51
    • FIGURE 3-4: Transition Timing for Entry to Sleep Mode

      51
    • FIGURE 3-5: Transition Timing for Wake from Sleep (HSPLL)

      52
    • 3.4.1 PRI_IDLE Mode

      52
    • 3.4.2 SEC_IDLE Mode

      52
      • FIGURE 3-6: Transition Timing for Entry to Idle Mode

        52
      • FIGURE 3-7: Transition Timing for Wake from Idle to Run Mode

        53
    • 3.4.3 RC_IDLE Mode

      53
  • 3.5 Exiting Idle and Sleep Modes

    54
    • 3.5.1 Exit by Interrupt

      54
    • 3.5.2 Exit by WDT Time-out

      54
    • 3.5.3 Exit by Reset

      54
    • 3.5.4 Exit without an Oscillator Start-up Delay

      54
  • 3.6 Selective Peripheral Module Control

    55
  • 3.7 Register Definitions: Peripheral Module Disable

    55
    • Register 3-1: PMD0: Peripheral Module Disable Register 0

      55
    • Register 3-2: PMD1: Peripheral Module Disable Register 1

      56
    • Register 3-3: PMD2: Peripheral Module Disable Register 2

      57
• 4.0 Reset

  59
  • 4.1 RCON Register

    59
    • FIGURE 4-1: Simplified Block Diagram of On-Chip Reset Circuit

      59
  • 4.2 Register Definitions: Reset Control

    60
    • Register 4-1: RCON: RESET Control Register

      60
  • 4.3 Master Clear (MCLR)

    61
  • 4.4 Power-on Reset (POR)

    61
    • FIGURE 4-2: External Power-on Reset Circuit (for Slow Vdd Power-up)

      61
  • 4.5 Brown-out Reset (BOR)

    62
    • 4.5.1 Detecting BOR

      62
    • 4.5.2 Software Enabled BOR

      62
    • 4.5.3 Disabling BOR in Sleep Mode

      62
    • 4.5.4 Minimum BOR Enable Time

      62
      • TABLE 4-1: BOR Configurations

        63
  • 4.6 Device Reset Timers

    63
    • 4.6.1 Power-up Timer (PWRT)

      63
    • 4.6.2 Oscillator Start-up Timer (OST)

      63
    • 4.6.3 PLL Lock Time-out

      63
    • 4.6.4 Time-out Sequence

      63
      • TABLE 4-2: Time-out in Various Situations

        64
      • FIGURE 4-3: Time-out Sequence on Power-up (MCLR Tied to Vdd, Vdd Rise < Tpwrt)

        64
      • FIGURE 4-4: Time-out Sequence on Power-up (MCLR not Tied to Vdd): Case 1

        64
      • FIGURE 4-5: Time-out Sequence on Power-up (Mclr not Tied to Vdd): Case 2

        65
      • FIGURE 4-6: Slow Rise Time (MCLR Tied to Vdd, Vdd Rise > Tpwrt)

        65
      • FIGURE 4-7: Time-out Sequence on Por w/PLL Enabled (MCLR Tied to Vdd)

        66
  • 4.7 Reset State of Registers

    67
    • TABLE 4-3: Status Bits, their Significance and the Initialization Condition for RCON Register

      67
    • TABLE 4-4: Registers Associated with Resets

      67
    • TABLE 4-5: Configuration Registers Associated with Resets

      68
• 5.0 Memory Organization

  69
  • 5.1 Program Memory Organization

    69
    • FIGURE 5-1: Program Memory Map and Stack for PIC18(L)F2X/4XK22 Devices

      70
    • 5.1.1 Program Counter

      70
    • 5.1.2 Return Address Stack

      70
      • FIGURE 5-2: Return Address Stack and Associated Registers

        71
  • 5.2 Register Definitions: Stack Pointer

    72
    • Register 5-1: STKPTR: Stack Pointer Register

      72
    • 5.2.1 Fast Register Stack

      72
      • EXAMPLE 5-1: Fast Register Stack Code Example

        73
    • 5.2.2 Look-up Tables in Program Memory

      73
      • EXAMPLE 5-2: Computed GOTO Using an Offset Value

        73
  • 5.3 PIC18 Instruction Cycle

    74
    • 5.3.1 Clocking Scheme

      74
    • 5.3.2 Instruction Flow/Pipelining

      74
      • FIGURE 5-3: Clock/ Instruction Cycle

        74
      • EXAMPLE 5-3: Instruction Pipeline Flow

        74
    • 5.3.3 Instructions in Program Memory

      75
      • FIGURE 5-4: Instructions in Program Memory

        75
    • 5.3.4 Two-Word Instructions

      75
      • EXAMPLE 5-4: Two-Word Instructions

        75
  • 5.4 Data Memory Organization

    76
    • 5.4.1 Bank Select Register (BSR)

      76
      • FIGURE 5-5: Data Memory Map for PIC18(L)F23K22 and PIC18(L)F43K22 Devices

        77
      • FIGURE 5-6: Data Memory Map for PIC18(L)F24K22 and PIC18(L)F44K22 Devices

        78
      • FIGURE 5-7: Data Memory Map for PIC18(L)F25K22 and PIC18(L)F45K22 Devices

        79
      • FIGURE 5-8: Data Memory Map for PIC18(L)F26K22 and PIC18(L)F46K22 Devices

        80
      • FIGURE 5-9: Use of the Bank Select Register (Direct Addressing)

        81
    • 5.4.2 Access Bank

      82
    • 5.4.3 General Purpose Register File

      82
    • 5.4.4 Special Function Registers

      82
      • TABLE 5-1: Special Function Register Map for PIC18(L)F2X/4XK22 Devices

        83
      • TABLE 5-2: Register File Summary for PIC18(L)F2X/4XK22 Devices

        84
    • 5.4.5 Status Register

      89
  • 5.5 Register Definitions: Status

    89
    • Register 5-2: STATUS: STATUS Register

      89
  • 5.6 Data Addressing Modes

    90
    • 5.6.1 Inherent and Literal Addressing

      90
    • 5.6.2 Direct Addressing

      90
    • 5.6.3 Indirect Addressing

      90
      • EXAMPLE 5-5: How to Clear Ram (Bank 1) Using Indirect Addressing

        90
      • FIGURE 5-10: Indirect Addressing

        91
  • 5.7 Data Memory and the Extended Instruction Set

    92
    • 5.7.1 Indexed Addressing with Literal Offset

      92
    • 5.7.2 Instructions Affected by Indexed Literal Offset Mode

      92
      • FIGURE 5-11: Comparing Addressing Options for Bit-Oriented and Byte-Oriented Instructions (Extended Instruction Set Enabled)

        93
    • 5.7.3 Mapping the Access Bank in Indexed Literal Offset Mode

      94
  • 5.8 PIC18 Instruction Execution and the Extended Instruction Set

    94
    • FIGURE 5-12: Remapping the Access Bank with Indexed Literal Offset Addressing

      94
• 6.0 Flash Program Memory

  95
  • 6.1 Table Reads and Table Writes

    95
    • FIGURE 6-1: Table Read Operation

      95
    • FIGURE 6-2: Table Write Operation

      96
  • 6.2 Control Registers

    96
    • 6.2.1 EECON1 and EECON2 Registers

      96
  • 6.3 Register Definitions: Memory Control

    97
    • Register 6-1: EECON1: Data EEPROM Control 1 Register

      97
    • 6.3.1 TABLAT – Table Latch Register

      98
    • 6.3.2 TBLPTR – Table Pointer Register

      98
    • 6.3.3 Table Pointer Boundaries

      98
      • TABLE 6-1: Table Pointer Operations with TBLRD and TBLWT Instructions

        98
      • FIGURE 6-3: Table Pointer Boundaries Based on Operation

        98
  • 6.4 Reading the Flash Program Memory

    99
    • FIGURE 6-4: Reads from Flash Program Memory

      99
    • EXAMPLE 6-1: Reading a Flash Program Memory Word

      99
  • 6.5 Erasing Flash Program Memory

    100
    • 6.5.1 Flash Program Memory Erase Sequence

      100
      • EXAMPLE 6-2: Erasing a Flash Program Memory block

        100
  • 6.6 Writing to Flash Program Memory

    101
    • FIGURE 6-5: Table Writes to Flash Program Memory

      101
    • 6.6.1 Flash Program Memory Write Sequence

      101
      • EXAMPLE 6-3: Writing to Flash Program Memory

        102
      • EXAMPLE 6-3: Writing to Flash Program Memory (Continued)

        103
    • 6.6.2 Write Verify

      103
    • 6.6.3 Unexpected Termination of Write Operation

      103
    • 6.6.4 Protection Against Spurious Writes

      103
  • 6.7 Flash Program Operation During Code Protection

    103
    • TABLE 6-2: Registers Associated with Program Flash Memory

      103
• 7.0 Data EEPROM Memory

  105
  • 7.1 EEADR and EEADRH Registers

    105
  • 7.2 EECON1 and EECON2 Registers

    105
    • Register 7-1: EECON1: Data EEPROM Control 1 Register

      106
  • 7.3 Reading the Data EEPROM Memory

    107
  • 7.4 Writing to the Data EEPROM Memory

    107
  • 7.5 Write Verify

    107
    • EXAMPLE 7-1: Data EEPROM Read

      107
    • EXAMPLE 7-2: Data EEPROM Write

      107
  • 7.6 Operation During Code-Protect

    108
  • 7.7 Protection Against Spurious Write

    108
  • 7.8 Using the Data EEPROM

    108
    • EXAMPLE 7-3: Data EEPROM Refresh Routine

      108
    • TABLE 7-1: Registers Associated with Data EEPROM Memory

      109
• 8.0 8 X 8 Hardware Multiplier

  111
  • 8.1 Introduction

    111
  • 8.2 Operation

    111
    • EXAMPLE 8-1: 8 x 8 Unsigned Multiply Routine

      111
    • EXAMPLE 8-2: 8 x 8 Signed Multiply Routine

      111
    • TABLE 8-1: Performance Comparison for Various Multiply Operations

      111
    • EQUATION 8-1: 16 x 16 Unsigned Multiplication Algorithm

      112
    • EXAMPLE 8-3: 16 x 16 Unsigned Multiply Routine

      112
    • EQUATION 8-2: 16 x 16 Signed Multiplication Algorithm

      112
    • EXAMPLE 8-4: 16 x 16 Signed Multiply Routine

      112
• 9.0 Interrupts

  113
  • 9.1 Mid-Range Compatibility

    113
  • 9.2 Interrupt Priority

    113
  • 9.3 Interrupt Response

    113
    • FIGURE 9-1: PIC18 Interrupt Logic

      114
  • 9.4 INTCON Registers

    115
  • 9.5 PIR Registers

    115
  • 9.6 PIE Registers

    115
  • 9.7 IPR Registers

    115
  • 9.8 Register Definitions: Interrupt Control

    116
    • Register 9-1: INTCON: Interrupt Control Register

      116
    • Register 9-2: INTCON2: Interrupt Control 2 Register

      117
    • Register 9-3: INTCON3: Interrupt Control 3 Register

      118
    • Register 9-4: PIR1: Peripheral Interrupt Request (Flag) Register 1

      119
    • Register 9-5: PIR2: Peripheral Interrupt Request (Flag) Register 2

      120
    • Register 9-6: PIR3: Peripheral Interrupt (Flag) Register 3

      121
    • Register 9-7: PIR4: Peripheral Interrupt (Flag) Register 4

      122
    • Register 9-8: PIR5: Peripheral Interrupt (Flag) Register 5

      123
    • Register 9-9: PIE1: Peripheral Interrupt Enable (Flag) Register 1

      124
    • Register 9-10: PIE2: Peripheral Interrupt Enable (Flag) Register 2

      125
    • Register 9-11: PIE3: Peripheral Interrupt Enable (Flag) Register 3

      126
    • Register 9-12: PIE4: Peripheral Interrupt Enable (Flag) Register 4

      127
    • Register 9-13: PIE5: Peripheral Interrupt Enable (Flag) Register 5

      127
    • Register 9-14: IPR1: Peripheral Interrupt Priority Register 1

      128
    • Register 9-15: IPR2: Peripheral Interrupt Priority Register 2

      129
    • Register 9-16: IPR3: Peripheral Interrupt Priority Register 3

      130
    • Register 9-17: IPR4: Peripheral Interrupt Priority Register 4

      131
    • Register 9-18: IPR5: Peripheral Interrupt Priority Register 5

      131
  • 9.9 INTn Pin Interrupts

    132
  • 9.10 TMR0 Interrupt

    132
  • 9.11 PORTB Interrupt-on-Change

    132
  • 9.12 Context Saving During Interrupts

    132
    • EXAMPLE 9-1: Saving Status, WREG and BSR Registers in RAM

      132
    • TABLE 9-1: Registers Associated with Interrupts

      133
    • TABLE 9-2: Configuration Registers Associated with Interrupts

      133
• 10.0 I/O Ports

  135
  • FIGURE 10-1: Generic I/O Port Operation

    135
  • 10.1 PORTA Registers

    135
    • EXAMPLE 10-1: Initializing PORTA

      135
    • TABLE 10-1: PORTA I/O Summary

      136
    • TABLE 10-2: Registers Associated with PORTA

      137
    • TABLE 10-3: Configuration Registers Associated with PORTA

      137
    • 10.1.1 PORTA Output Priority

      138
      • TABLE 10-4: Port Pin Function Priority

        138
  • 10.2 PORTB Registers

    140
    • EXAMPLE 10-2: Initializing PORTB

      140
    • 10.2.1 PORTB Output Priority

      140
  • 10.3 Additional PORTB Pin Functions

    140
    • 10.3.1 Weak Pull-Ups

      140
    • 10.3.2 Interrupt-On-Change

      140
    • 10.3.3 Alternate Functions

      141
      • TABLE 10-5: PORTB I/O Summary

        141
      • TABLE 10-6: Registers Associated with PORTB

        143
      • TABLE 10-7: Configuration Registers Associated with PORTB

        144
  • 10.4 PORTC Registers

    144
    • EXAMPLE 10-3: Initializing PORTC

      144
    • 10.4.1 PORTC Output Priority

      144
      • TABLE 10-8: PORTC I/O Summary

        145
      • TABLE 10-9: Registers Associated with PORTC

        147
      • TABLE 10-10: Configuration Registers Associated with PORTC

        147
  • 10.5 PORTD Registers

    148
    • EXAMPLE 10-4: Initializing PORTD

      148
    • 10.5.1 PORTD Output Priority

      148
      • TABLE 10-11: PORTD I/O Summary

        149
      • TABLE 10-12: Registers Associated with PORTD

        150
      • TABLE 10-13: Configuration Registers Associated with PORTD

        150
  • 10.6 PORTE Registers

    151
    • 10.6.1 PORTE on 40/44-Pin Devices

      151
      • EXAMPLE 10-5: Initializing PORTE

        151
    • 10.6.2 PORTE on 28-Pin Devices

      151
    • 10.6.3 RE3 Weak Pull-Up

      151
    • 10.6.4 PORTE Output Priority

      151
      • TABLE 10-14: PORTE I/O Summary

        152
      • TABLE 10-15: Registers Associated with PORTE

        152
      • TABLE 10-16: Configuration Registers Associated with PORTE

        153
  • 10.7 Port Analog Control

    153
  • 10.8 Port Slew Rate Control

    153
  • 10.9 Register Definitions – Port Control

    153
    • Register 10-1: PORTx(1): PORTx Register

      153
    • Register 10-2: PORTE: PORTE Register

      154
    • Register 10-3: ANSELA – PORTA Analog Select Register

      154
    • Register 10-4: ANSELB – PORTB Analog Select Register

      155
    • Register 10-5: ANSELC – PORTC Analog Select Register

      155
    • Register 10-6: ANSELD – PORTD Analog Select Register

      155
    • Register 10-7: ANSELE – PORTE Analog Select Register

      156
    • Register 10-8: TRISx: PORTx Tri-State Register(1)

      156
    • Register 10-9: TRISE: PORTE Tri-State Register

      156
    • Register 10-10: LATx: Portx Output Latch Register(1)

      157
    • Register 10-11: LATE: PORTE Output Latch Register(1)

      157
    • Register 10-12: WPUB: Weak Pull-up PORTB Register

      157
    • Register 10-13: IOCB: Interrupt-on-Change PORTB Control register

      158
    • Register 10-14: SLRCON: Slew Rate Control Register

      158
• 11.0 Timer0 Module

  159
  • 11.1 Register Definitions: Timer0 Control

    159
    • Register 11-1: T0CON: Timer0 Control Register

      159
  • 11.2 Timer0 Operation

    160
  • 11.3 Timer0 Reads and Writes in 16-Bit Mode

    160
    • FIGURE 11-1: Timer0 Block Diagram (8-Bit Mode)

      160
    • FIGURE 11-2: Timer0 Block Diagram (16-Bit Mode)

      161
  • 11.4 Prescaler

    161
    • 11.4.1 Switching Prescaler Assignment

      161
  • 11.5 Timer0 Interrupt

    161
    • TABLE 11-1: Registers Associated with Timer0

      161
• 12.0 Timer1/3/5 Module with Gate Control

  163
  • FIGURE 12-1: Timer1/3/5 Block Diagram

    163
  • 12.1 Timer1/3/5 Operation

    164
    • TABLE 12-1: Timer1/3/5 Enable Selections

      164
  • 12.2 Clock Source Selection

    164
    • 12.2.1 Internal Clock Source

      164
    • 12.2.2 External Clock Source

      164
      • TABLE 12-2: Clock Source Selections

        164
  • 12.3 Timer1/3/5 Prescaler

    165
  • 12.4 Secondary Oscillator

    165
  • 12.5 Timer1/3/5 Operation in Asynchronous Counter Mode

    165
    • 12.5.1 Reading and Writing Timer1/3/5 in Asynchronous Counter Mode

      165
  • 12.6 Timer1/3/5 16-Bit Read/Write Mode

    165
    • FIGURE 12-2: Timer1/3/5 16-Bit Read/Write Mode Block Diagram

      166
  • 12.7 Timer1/3/5 Gate

    166
    • 12.7.1 Timer1/3/5 Gate Enable

      166
      • TABLE 12-3: Timer1/3/5 Gate Enable Selections

        166
    • 12.7.2 Timer1/3/5 Gate Source Selection

      166
      • TABLE 12-4: Timer1/3/5 Gate Sources

        166
      • TABLE 12-5: Gate Resources for Timer2/4/6 Match to PR2/4/6

        166
    • 12.7.3 Timer1/3/5 Gate Toggle Mode

      167
    • 12.7.4 Timer1/3/5 Gate Single-Pulse Mode

      167
    • 12.7.5 Timer1/3/5 Gate Value Status

      167
    • 12.7.6 Timer1/3/5 Gate Event Interrupt

      167
  • 12.8 Timer1/3/5 Interrupt

    168
  • 12.9 Timer1/3/5 Operation During Sleep

    168
  • 12.10 ECCP/CCP Capture/Compare Time Base

    168
  • 12.11 ECCP/CCP Special Event Trigger

    168
    • FIGURE 12-3: Timer1/3/5 Incrementing Edge

      169
    • FIGURE 12-4: Timer1/3/5 Gate Enable Mode

      169
    • FIGURE 12-5: Timer1/3/5 Gate Toggle Mode

      170
    • FIGURE 12-6: Timer1/3/5 Gate Single-Pulse Mode

      170
    • FIGURE 12-7: Timer1/3/5 Gate Single-Pulse and Toggle Combined Mode

      171
  • 12.12 Peripheral Module Disable

    171
  • 12.13 Register Definitions: Timer1/3/5 Control

    172
    • Register 12-1: TxCON: Timer1/3/5 Control Register

      172
    • Register 12-2: TxGCON: Timer1/3/5 Gate Control Register

      173
    • TABLE 12-6: Registers Associated with Timer1/3/5 as a Timer/Counter

      174
    • TABLE 12-7: Configuration Registers Associated with Timer1/3/5

      174
• 13.0 Timer2/4/6 Module

  175
  • FIGURE 13-1: Timer2/4/6 Block Diagram

    175
  • 13.1 Timer2/4/6 Operation

    176
  • 13.2 Timer2/4/6 Interrupt

    176
  • 13.3 Timer2/4/6 Output

    176
  • 13.4 Timer2/4/6 Operation During Sleep

    176
  • 13.5 Peripheral Module Disable

    176
  • 13.6 Register Definitions: Timer2/4/6 Control

    177
    • Register 13-1: TxCON: Timer2/Timer4/Timer6 Control Register

      177
    • TABLE 13-1: Summary of Registers Associated With Timer2/4/6

      178
• 14.0 Capture/Compare/PWM Modules

  179
  • TABLE 14-1: PWM Resources

    179
  • 14.1 Capture Mode

    180
    • FIGURE 14-1: Capture Mode Operation Block Diagram

      180
    • 14.1.1 CCP pin Configuration

      180
      • TABLE 14-2: CCP Pin Multiplexing

        180
    • 14.1.2 Timer1 Mode Resource

      180
    • 14.1.3 Software Interrupt Mode

      180
    • 14.1.4 CCP Prescaler

      181
      • EXAMPLE 14-1: Changing Between Capture Prescalers

        181
    • 14.1.5 Capture During Sleep

      181
      • TABLE 14-3: Registers Associated with Capture

        181
      • TABLE 14-4: Configuration Registers Associated with Capture

        182
  • 14.2 Compare Mode

    183
    • FIGURE 14-2: Compare Mode Operation Block Diagram

      183
    • 14.2.1 CCP Pin Configuration

      183
    • 14.2.2 Timerx Mode Resource

      183
    • 14.2.3 Software Interrupt Mode

      183
    • 14.2.4 Special Event Trigger

      184
    • 14.2.5 Compare During Sleep

      184
      • TABLE 14-5: Registers Associated with Compare

        184
      • TABLE 14-6: Configuration Registers Associated with Compare

        185
  • 14.3 PWM Overview

    186
    • 14.3.1 Standard PWM Operation

      186
      • FIGURE 14-3: CCP PWM Output Signal

        186
      • FIGURE 14-4: Simplified PWM Block Diagram

        186
    • 14.3.2 Setup for PWM Operation

      186
    • 14.3.3 PWM Timer Resource

      187
    • 14.3.4 PWM Period

      187
      • EQUATION 14-1: PWM Period

        187
    • 14.3.5 PWM Duty Cycle

      187
      • EQUATION 14-2: Pulse Width

        187
      • EQUATION 14-3: Duty Cycle Ratio

        187
    • 14.3.6 PWM Resolution

      188
      • EQUATION 14-4: PWM Resolution

        188
      • TABLE 14-7: Example PWM Frequencies and Resolutions (Fosc = 32 MHz)

        188
      • TABLE 14-8: Example PWM Frequencies and Resolutions (Fosc = 20 MHz)

        188
      • TABLE 14-9: Example PWM Frequencies and Resolutions (Fosc = 8 MHz)

        188
    • 14.3.7 Operation in Sleep Mode

      188
    • 14.3.8 Changes in System Clock Frequency

      188
    • 14.3.9 Effects of Reset

      188
      • TABLE 14-10: Registers Associated with Standard PWM

        189
      • TABLE 14-11: Configuration Registers Associated with Standard PWM

        189
  • 14.4 PWM (Enhanced Mode)

    190
    • FIGURE 14-5: Example Simplified Block Diagram of the Enhanced PWM Mode

      190
    • TABLE 14-12: Example Pin Assignments for Various PWM Enhanced Modes

      191
    • FIGURE 14-6: Example PWM (Enhanced Mode) Output Relationships (Active-High State)

      191
    • FIGURE 14-7: Example Enhanced PWM Output Relationships (Active-Low State)

      192
    • 14.4.1 Half-Bridge Mode

      193
      • FIGURE 14-8: Example of Half- Bridge PWM Output

        193
      • FIGURE 14-9: Example of Half-Bridge Applications

        193
    • 14.4.2 Full-Bridge Mode

      194
      • FIGURE 14-10: Example of Full-Bridge Application

        194
      • FIGURE 14-11: Example of Full-Bridge PWM Output

        195
      • FIGURE 14-12: Example of PWM Direction Change

        196
      • FIGURE 14-13: Example of PWM Direction Change at Near 100% Duty Cycle

        197
    • 14.4.3 Enhanced PWM Auto- shutdown Mode

      197
      • FIGURE 14-14: PWM Auto-shutdown With Firmware Restart (PxRSEN = 0)

        198
    • 14.4.4 Auto-Restart Mode

      198
      • FIGURE 14-15: PWM Auto-shutdown With Auto-Restart (PxRSEN = 1)

        198
    • 14.4.5 Programmable Dead-Band Delay Mode

      199
      • FIGURE 14-16: Example of Half- Bridge PWM Output

        199
      • FIGURE 14-17: Example of Half-Bridge Applications

        199
    • 14.4.6 PWM Steering Mode

      200
      • FIGURE 14-18: Simplified Steering Block Diagram

        200
    • 14.4.7 Start-up Considerations

      201
      • FIGURE 14-19: Example of Steering Event at End of Instruction (STRxSYNC = 0)

        201
      • FIGURE 14-20: Example of Steering Event at Beginning of Instruction (STRxSYNC = 1)

        201
    • 14.4.8 SETUP FOR ECCP PWM OPERATION using ECCP1 and Timer2

      202
      • TABLE 14-13: Registers Associated with Enhanced PWM

        203
      • TABLE 14-14: Configuration Registers Associated with Enhanced PWM

        204
  • 14.5 Register Definitions: ECCP Control

    205
    • Register 14-1: CCPXCON: Standard CCPx Control Register

      205
    • Register 14-2: CCPxCON: Enhanced CCPx Control Register

      206
    • Register 14-3: CCPTMRS0: PWM Timer Selection Control Register 0

      208
    • Register 14-4: CCPTMRS1: PWM Timer Selection Control Register 1

      208
    • Register 14-5: ECCPxAS: CCPx Auto-Shutdown Control Register

      209
    • Register 14-6: PWMxCON: Enhanced PWM Control Register

      210
    • Register 14-7: PSTRxCON: PWM Steering Control Register(1)

      210
• 15.0 Master Synchronous Serial Port (MSSP1 and MSSP2) Module

  211
  • 15.1 Master SSPx (MSSPx) Module Overview

    211
    • FIGURE 15-1: MSSPx Block Diagram (SPI mode)

      211
    • FIGURE 15-2: MSSPx Block Diagram (I2C™ Master mode)

      212
    • FIGURE 15-3: MSSPx Block Diagram (I2C™ Slave mode)

      213
  • 15.2 SPI Mode Overview

    214
    • FIGURE 15-4: SPI Master and Multiple Slave Connection

      215
    • 15.2.1 SPI Mode Registers

      215
    • 15.2.2 SPI Mode Operation

      215
      • FIGURE 15-5: SPI Master/Slave Connection

        216
    • 15.2.3 SPI Master Mode

      217
      • FIGURE 15-6: SPI Mode Waveform (Master Mode)

        217
    • 15.2.4 SPI Slave Mode

      218
    • 15.2.5 Slave Select Synchronization

      218
      • FIGURE 15-7: SPI Daisy-Chain Connection

        219
      • FIGURE 15-8: Slave Select Synchronous Waveform

        219
      • FIGURE 15-9: SPI Mode Waveform (Slave Mode With CKE = 0)

        220
      • FIGURE 15-10: SPI Mode Waveform (SLAve Mode With CKE = 1)

        220
    • 15.2.6 SPI Operation IN Sleep Mode

      221
      • TABLE 15-1: Registers Associated with SPI Operation

        221
  • 15.3 I2C Mode Overview

    222
    • FIGURE 15-11: I2C™ Master/ Slave Connection

      222
    • 15.3.1 Clock Stretching

      223
    • 15.3.2 Arbitration

      223
  • 15.4 I2C Mode Operation

    224
    • 15.4.1 Byte Format

      224
    • 15.4.2 Definition of I2C Terminology

      224
    • 15.4.3 SDAx and SCLx Pins

      224
    • 15.4.4 SDAx Hold Time

      224
      • TABLE 15-2: I2C™ Bus Terms

        224
    • 15.4.5 Start Condition

      225
    • 15.4.6 STOP Condition

      225
    • 15.4.7 Restart Condition

      225
    • 15.4.8 START/STOP Condition Interrupt Masking

      225
      • FIGURE 15-12: I2C™ Start and Stop Conditions

        225
      • FIGURE 15-13: I2C™ Restart Condition

        225
    • 15.4.9 Acknowledge Sequence

      226
  • 15.5 I2C Slave Mode Operation

    226
    • 15.5.1 Slave Mode Addresses

      226
    • 15.5.2 Slave Reception

      227
      • FIGURE 15-14: I2C Slave, 7-Bit Address, Reception (SEN = 0, AHEN = 0, DHEN = 0)

        228
      • FIGURE 15-15: I2C Slave, 7-Bit Address, Reception (SEN = 1, AHEN = 0, DHEN = 0)

        229
      • FIGURE 15-16: I2C Slave, 7-Bit Address, Reception (SEN = 0, AHEN = 1, DHEN = 1)

        230
      • FIGURE 15-17: I2C Slave, 7-Bit Address, Reception (SEN = 1, AHEN = 1, DHEN = 1)

        231
    • 15.5.3 SLAVE Transmission

      232
      • FIGURE 15-18: I2C Slave, 7-Bit Address, Transmission (AHEN = 0)

        233
      • FIGURE 15-19: I2C Slave, 7-Bit Address, Transmission (AHEN = 1)

        235
    • 15.5.4 Slave Mode 10-bit Address Reception

      236
    • 15.5.5 10-bit Addressing With Address Or Data Hold

      236
      • FIGURE 15-20: I2C Slave, 10-Bit Address, Reception (SEN = 1, AHEN = 0, DHEN = 0)

        237
      • FIGURE 15-21: I2C Slave, 10-Bit Address, Reception (SeN = 0, AHEN = 1, DHEN = 0)

        238
      • FIGURE 15-22: I2C Slave, 10-Bit Address, Transmission (SEN = 0, AHEN = 0, DHEN = 0)

        239
    • 15.5.6 Clock Stretching

      240
    • 15.5.7 Clock Synchronization and the CKP bit

      240
      • FIGURE 15-23: Clock Synchronization Timing

        240
    • 15.5.8 General Call Address Support

      241
      • FIGURE 15-24: Slave Mode General Call Address Sequence

        241
    • 15.5.9 SSPx Mask Register

      241
  • 15.6 I2C Master Mode

    242
    • 15.6.1 I2C Master Mode Operation

      242
    • 15.6.2 Clock Arbitration

      243
      • FIGURE 15-25: Baud Rate Generator Timing with Clock Arbitration

        243
    • 15.6.3 WCOL Status Flag

      243
    • 15.6.4 I2C Master Mode Start Condition Timing

      244
      • FIGURE 15-26: First Start Bit Timing

        244
    • 15.6.5 I2C Master Mode Repeated Start Condition Timing

      245
      • FIGURE 15-27: Repeat Start Condition Waveform

        245
    • 15.6.6 I2C Master Mode Transmission

      246
      • FIGURE 15-28: I2C Master Mode Waveform (Transmission, 7 or 10-Bit Address)

        247
    • 15.6.7 I2C Master Mode Reception

      248
      • FIGURE 15-29: I2C™ Master Mode Waveform (Reception, 7-Bit Address)

        249
    • 15.6.8 Acknowledge Sequence Timing

      250
    • 15.6.9 Stop Condition Timing

      250
      • FIGURE 15-30: Acknowledge Sequence Waveform

        250
      • FIGURE 15-31: Stop Condition Receive or Transmit Mode

        251
    • 15.6.10 Sleep Operation

      251
    • 15.6.11 Effects of a Reset

      251
    • 15.6.12 Multi-Master Mode

      251
    • 15.6.13 Multi -Master Communication, Bus Collision and Bus Arbitration

      252
      • FIGURE 15-32: Bus Collision Timing for Transmit and Acknowledge

        252
      • FIGURE 15-33: Bus Collision During Start Condition (SDAx Only)

        253
      • FIGURE 15-34: Bus Collision During Start Condition (SCLx = 0)

        254
      • FIGURE 15-35: BRG Reset Due to Sda Arbitration During Start Condition

        254
      • FIGURE 15-36: Bus Collision During a Repeated Start Condition (Case 1)

        255
      • FIGURE 15-37: Bus Collision During Repeated Start Condition (Case 2)

        255
      • FIGURE 15-38: Bus Collision During a Stop Condition (Case 1)

        256
      • FIGURE 15-39: Bus Collision During a Stop Condition (Case 2)

        256
      • TABLE 15-3: Registers Associated with I2C™ Operation

        257
  • 15.7 Baud Rate Generator

    258
    • EQUATION 15-1:

      258
    • FIGURE 15-40: Baud Rate Generator Block Diagram

      258
    • TABLE 15-4: MSSPx Clock Rate w/BRG

      258
  • 15.8 Register Definitions: MSSP Control

    259
    • Register 15-1: SSPxSTAT: SSPx STATUS Register

      259
    • Register 15-2: SSPxCON1: SSPx Control Register 1

      260
    • Register 15-3: SSPxCON2: SSPx Control Register 2

      262
    • Register 15-4: SSPxCON3: SSPx Control Register 3

      263
    • Register 15-5: SSPxMSK: SSPx Mask Register

      264
    • Register 15-6: SSPxADD: MSSPx Address and Baud Rate Register (I2C Mode)

      265
• 16.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART)

  267
  • FIGURE 16-1: EUSART Transmit Block Diagram

    267
  • FIGURE 16-2: EUSART Receive Block Diagram

    268
  • 16.1 EUSART Asynchronous Mode

    269
    • 16.1.1 EUSART Asynchronous Transmitter

      269
      • FIGURE 16-3: Asynchronous Transmission

        270
      • FIGURE 16-4: Asynchronous Transmission (Back-to-Back)

        271
      • TABLE 16-1: Registers Associated with Asynchronous Transmission

        271
    • 16.1.2 EUSART Asynchronous Receiver

      272
      • FIGURE 16-5: Asynchronous Reception

        275
      • TABLE 16-2: Registers Associated with Asynchronous Reception

        275
  • 16.2 Clock Accuracy with Asynchronous Operation

    276
  • 16.3 Register Definitions: EUSART Control

    277
    • Register 16-1: TXSTAx: Transmit Status AND Control REGISTER

      277
    • Register 16-2: RCSTAx: Receive Status and Control Register

      278
    • Register 16-3: BAUDCONx: Baud Rate Control Register

      279
  • 16.4 EUSART Baud Rate Generator (BRG)

    280
    • EXAMPLE 16-1: Calculating Baud Rate Error

      280
    • TABLE 16-3: Baud Rate Formulas

      280
    • TABLE 16-4: Registers Associated with Baud Rate Generator

      281
    • TABLE 16-5: BAUD Rates for Asynchronous Modes

      281
    • 16.4.1 Auto-Baud Detect

      284
      • TABLE 16-6: BRG Counter Clock Rates

        284
      • FIGURE 16-6: Automatic Baud Rate Calibration

        284
    • 16.4.2 Auto-baud Overflow

      285
    • 16.4.3 Auto-Wake-up on Break

      285
      • FIGURE 16-7: Auto-Wake-up Bit (WUE) Timing During Normal Operation

        286
      • FIGURE 16-8: Auto-Wake-up Bit (WUE) Timings During Sleep

        286
    • 16.4.4 BREAK Character Sequence

      287
    • 16.4.5 Receiving a BREAK Character

      287
      • FIGURE 16-9: Send Break Character Sequence

        287
  • 16.5 EUSART Synchronous Mode

    288
    • 16.5.1 Synchronous Master Mode

      288
      • FIGURE 16-10: Synchronous Transmission

        289
      • FIGURE 16-11: Synchronous Transmission (Through TXEN)

        289
      • TABLE 16-7: Registers Associated with Synchronous Master Transmission

        290
      • FIGURE 16-12: Synchronous Reception (Master Mode, SREN)

        292
      • TABLE 16-8: Registers Associated with Synchronous Master Reception

        292
    • 16.5.2 Synchronous Slave Mode

      293
      • TABLE 16-9: Registers Associated with Synchronous Slave Transmission

        294
      • TABLE 16-10: Registers Associated with Synchronous Slave Reception

        295
• 17.0 Analog-to-Digital Converter (ADC) Module

  297
  • FIGURE 17-1: ADC Block Diagram

    297
  • 17.1 ADC Configuration

    298
    • 17.1.1 Port Configuration

      298
    • 17.1.2 Channel Selection

      298
    • 17.1.3 ADC Voltage Reference

      298
    • 17.1.4 Selecting and Configuring Acquisition Time

      298
    • 17.1.5 Conversion Clock

      299
    • 17.1.6 Interrupts

      299
      • TABLE 17-1: ADC Clock Period (Tad) Vs. Device Operating Frequencies

        299
    • 17.1.7 Result Formatting

      300
      • FIGURE 17-2: 10-Bit A/D Conversion Result Format

        300
  • 17.2 ADC Operation

    301
    • 17.2.1 Starting a Conversion

      301
      • FIGURE 17-3: A/D Conversion Tad Cycles (ACQT<2:0> = 000, TACQ = 0)

        301
      • FIGURE 17-4: A/D Conversion Tad Cycles (ACQT<2:0> = 010, TACQ = 4 TAD)

        301
    • 17.2.2 Completion of a Conversion

      302
    • 17.2.3 Discharge

      302
    • 17.2.4 Terminating a conversion

      302
    • 17.2.5 Delay Between Conversions

      302
    • 17.2.6 ADC Operation in Power- Managed Modes

      302
    • 17.2.7 ADC Operation During Sleep

      302
    • 17.2.8 Special Event Trigger

      302
    • 17.2.9 Peripheral Module Disable

      302
    • 17.2.10 A/D Conversion Procedure

      303
      • EXAMPLE 17-1: A/D Conversion

        303
  • 17.3 Register Definitions: ADC Control

    304
    • Register 17-1: ADCON0: A/D Control Register 0

      304
    • Register 17-2: ADCON1: A/D Control Register 1

      305
    • Register 17-3: ADCON2: A/D Control Register 2

      306
    • Register 17-4: ADRESH: ADC Result Register High (ADRESH) ADFM = 0

      307
    • Register 17-5: ADRESL: ADC Result Register Low (ADRESL) ADFM = 0

      307
    • Register 17-6: ADRESH: ADC Result Register High (ADRESH) ADFM = 1

      307
    • Register 17-7: ADRESL: ADC Result Register Low (ADRESL) ADFM = 1

      307
  • 17.4 A/D Acquisition Requirements

    308
    • EQUATION 17-1: Acquisition Time Example

      308
    • FIGURE 17-5: Analog Input Model

      309
    • FIGURE 17-6: ADC Transfer Function

      309
    • TABLE 17-2: Registers Associated with A/D Operation

      310
    • TABLE 17-3: Configuration Registers Associated with the ADC Module

      310
• 18.0 Comparator Module

  311
  • 18.1 Comparator Overview

    311
    • FIGURE 18-1: Single Comparator

      311
    • FIGURE 18-2: Comparator C1/C2 Simplified Block Diagram

      312
  • 18.2 Comparator Control

    313
    • 18.2.1 Comparator Enable

      313
    • 18.2.2 Comparator Input Selection

      313
    • 18.2.3 Comparator Reference Selection

      313
    • 18.2.4 Comparator Output Selection

      313
    • 18.2.5 Comparator Output Polarity

      313
      • TABLE 18-1: Comparator Output State vs. Input Conditions

        313
    • 18.2.6 Comparator Speed Selection

      313
  • 18.3 Comparator Response Time

    313
  • 18.4 Comparator Interrupt Operation

    314
    • 18.4.1 Presetting the Mismatch Latches

      314
      • FIGURE 18-3: Comparator Interrupt Timing W/O CMxCON0 Read

        314
      • FIGURE 18-4: Comparator Interrupt Timing With CMxCON0 Read

        314
  • 18.5 Operation During Sleep

    315
  • 18.6 Effects of a Reset

    315
  • 18.7 Analog Input Connection Considerations

    315
    • FIGURE 18-5: Analog Input Model

      315
  • 18.8 Additional Comparator Features

    316
    • 18.8.1 Simultaneous Comparator Output Read

      316
    • 18.8.2 Internal Reference Selection

      316
    • 18.8.3 Comparator Hysteresis

      316
    • 18.8.4 Synchronizing Comparator Output to Timer1

      316
  • 18.9 Register Definitions: Comparator Control

    317
    • Register 18-1: CMxCON0: Comparator x Control Register

      317
    • Register 18-2: CM2CON1: Comparator 1 and 2 Control Register

      318
    • TABLE 18-2: Registers Associated with Comparator Module

      319
• 19.0 Charge Time Measurement Unit (CTMU)

  321
  • FIGURE 19-1: CTMU Block Diagram

    321
  • 19.1 CTMU Operation

    322
    • 19.1.1 Theory of Operation

      322
    • 19.1.2 Current Source

      322
    • 19.1.3 Edge Selection and Control

      322
    • 19.1.4 Edge Status

      322
    • 19.1.5 Interrupts

      323
  • 19.2 CTMU Module Initialization

    323
  • 19.3 Calibrating the CTMU Module

    324
    • 19.3.1 Current Source Calibration

      324
      • FIGURE 19-2: CTMU Current Source Calibration Circuit

        324
      • EXAMPLE 19-1: Setup for CTMU Calibration Routines

        325
      • EXAMPLE 19-2: Current Calibration Routine

        326
    • 19.3.2 Capacitance Calibration

      327
      • EXAMPLE 19-3: Capacitance Calibration Routine

        328
  • 19.4 Measuring Capacitance with the CTMU

    329
    • 19.4.1 Absolute Capacitance Measurement

      329
    • 19.4.2 Relative Charge Measurement

      329
      • EXAMPLE 19-4: Routine for Capacitive Touch Switch

        330
  • 19.5 Measuring Time with the CTMU Module

    331
    • FIGURE 19-3: Typical Connections and Internal Configuration for Time Measurement

      331
  • 19.6 Creating a Delay with the CTMU Module

    332
    • FIGURE 19-4: Typical Connections and Internal Configuration for Pulse Delay Generation

      332
  • 19.7 Operation During Sleep/Idle Modes

    332
    • 19.7.1 Sleep Mode and Deep Sleep Modes

      332
    • 19.7.2 Idle Mode

      332
  • 19.8 CTMU Peripheral Module Disable (PMD)

    332
  • 19.9 Effects of a Reset on CTMU

    333
  • 19.10 Registers

    333
  • 19.11 Register Definitions: CTMU Control

    333
    • Register 19-1: CTMUCONH: CTMU Control Register 0

      333
    • Register 19-2: CTMUCONL: CTMU Control Register 1

      334
    • Register 19-3: CTMUICON: CTMU current Control Register

      335
    • TABLE 19-1: Registers Associated with CTMU Module

      335
• 20.0 SR Latch

  337
  • 20.1 Latch Operation

    337
  • 20.2 Latch Output

    337
  • 20.3 DIVSRCLK Clock Generation

    337
  • 20.4 Effects of a Reset

    337
    • FIGURE 20-1: DIVSRCLK Block Diagram

      338
    • FIGURE 20-2: SR Latch Simplified Block Diagram

      338
    • TABLE 20-1: DIVSRCLK Frequency table

      339
  • 20.5 Register Definitions: SR Latch Control

    340
    • Register 20-1: SRCON0: SR Latch Control Register

      340
    • Register 20-2: SRCON1: SR Latch Control Register 1

      341
    • TABLE 20-2: Registers Associated with the SR Latch

      341
• 21.0 Fixed Voltage Reference (FVR)

  343
  • 21.1 Independent Gain Amplifiers

    343
  • 21.2 FVR Stabilization Period

    343
    • FIGURE 21-1: Voltage Reference Block Diagram

      343
  • 21.3 Register Definitions: FVR Control

    344
    • Register 21-1: VREFCON0: Fixed Voltage Reference Control Register

      344
    • TABLE 21-1: Summary of Registers Associated with Fixed Voltage Reference

      344
• 22.0 Digital-to-Analog Converter (DAC) Module

  345
  • 22.1 Output Voltage Selection

    345
    • EQUATION 22-1: DAC Output Voltage

      345
  • 22.2 Ratiometric Output Level

    345
  • 22.3 Low-Power Voltage State

    345
  • 22.4 Output Clamped to Positive Voltage Source

    345
  • 22.5 Output Clamped to Negative Voltage Source

    345
  • 22.6 DAC Voltage Reference Output

    345
    • FIGURE 22-1: Digital-to-Analog Converter Block Diagram

      346
    • FIGURE 22-2: Voltage Reference Output Buffer Example

      346
  • 22.7 Operation During Sleep

    347
  • 22.8 Effects of a Reset

    347
  • 22.9 Register Definitions: DAC Control

    347
    • Register 22-1: VREFCON1: Voltage Reference Control Register 0

      347
    • Register 22-2: VREFCON2: Voltage Reference Control Register 1

      348
    • TABLE 22-1: Registers Associated with DAC Module

      348
• 23.0 High/Low-Voltage Detect (HLVD)

  349
  • 23.1 Register - HLVD Control

    349
    • Register 23-1: HLVDCON: High/Low-Voltage Detect Control Register

      349
  • 23.2 Operation

    350
    • FIGURE 23-1: HLVD Module Block Diagram (with External Input)

      350
  • 23.3 HLVD Setup

    351
  • 23.4 Current Consumption

    351
  • 23.5 HLVD Start-up Time

    351
    • FIGURE 23-2: Low-Voltage Detect Operation (VDIRMAG = 0)

      351
    • FIGURE 23-3: High-Voltage Detect Operation (VDIRMAG = 1)

      352
  • 23.6 Applications

    352
    • FIGURE 23-4: Typical Low-Voltage Detect Application

      352
  • 23.7 Operation During Sleep

    353
  • 23.8 Effects of a Reset

    353
    • TABLE 23-1: Registers Associated with High/Low-Voltage Detect Module

      353
• 24.0 Special Features of the CPU

  355
  • 24.1 Configuration Bits

    355
    • TABLE 24-1: Configuration Bits and Device IDs

      356
  • 24.2 Register Definitions: Configuration Word

    357
    • Register 24-1: CONFIG1H: Configuration Register 1 High

      357
    • Register 24-2: CONFIG2L: Configuration Register 2 Low

      358
    • Register 24-3: CONFIG2H: Configuration Register 2 High

      359
    • Register 24-4: CONFIG3H: Configuration Register 3 High

      360
    • Register 24-5: CONFIG4L: Configuration Register 4 Low

      361
    • Register 24-6: CONFIG5L: Configuration Register 5 Low

      361
    • Register 24-7: CONFIG5H: Configuration Register 5 High

      362
    • Register 24-8: CONFIG6L: Configuration Register 6 Low

      362
    • Register 24-9: CONFIG6H: Configuration Register 6 High

      363
    • Register 24-10: CONFIG7L: Configuration Register 7 Low

      363
    • Register 24-11: CONFIG7H: Configuration Register 7 High

      364
    • Register 24-12: DEVID1: Device ID Register 1

      364
    • Register 24-13: DEVID2: Device ID Register 2

      364
    • TABLE 24-2: Device ID Table for the PIC18(L)F2X/4XK22 Family

      365
  • 24.3 Watchdog Timer (WDT)

    366
    • FIGURE 24-1: WDT Block Diagram

      366
    • 24.3.1 Control Register

      367
  • 24.4 Register Definitions: WDT Control

    367
    • Register 24-14: WDTCON: Watchdog Timer Control Register

      367
    • TABLE 24-3: Registers Associated with Watchdog Timer

      367
    • TABLE 24-4: Configuration Registers Associated with Watchdog Timer

      367
  • 24.5 Program Verification and Code Protection

    368
    • FIGURE 24-2: Code-Protected Program Memory for PIC18(L)F2X/4XK22

      368
    • TABLE 24-5: Configuration Registers Associated with Code Protection

      368
    • 24.5.1 Program Memory Code Protection

      369
      • FIGURE 24-3: Table Write (WRTn) Disallowed

        369
      • FIGURE 24-4: External Block Table Read (EBTRn) Disallowed

        370
      • FIGURE 24-5: External Block Table Read (EBTRn) Allowed

        370
    • 24.5.2 Data EEPROM Code Protection

      371
    • 24.5.3 Configuration Register Protection

      371
  • 24.6 ID Locations

    371
  • 24.7 In-Circuit Serial Programming

    371
  • 24.8 In-Circuit Debugger

    371
    • TABLE 24-6: Debugger Resources

      371
  • 24.9 Single-Supply ICSP Programming

    371
• 25.0 Instruction Set Summary

  373
  • 25.1 Standard Instruction Set

    373
    • TABLE 25-1: Opcode Field Descriptions

      374
    • FIGURE 25-1: General Format for Instructions

      375
    • TABLE 25-2: PIC18(L)F2X/4XK22 Instruction Set

      376
    • 25.1.1 Standard Instruction Set

      379
  • 25.2 Extended Instruction Set

    415
    • 25.2.1 Extended Instruction Syntax

      415
      • TABLE 25-3: Extensions to the PIC18 Instruction Set

        415
    • 25.2.2 Extended Instruction Set

      416
    • 25.2.3 Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode

      420
    • 25.2.4 Considerations when Enabling the Extended Instruction Set

      420
    • 25.2.5 Special Considerations with Microchip MPLAB® IDE Tools

      422
• 26.0 Development Support

  423
  • 26.1 MPLAB Integrated Development Environment Software

    423
  • 26.2 MPLAB C Compilers for Various Device Families

    424
  • 26.3 HI-TECH C for Various Device Families

    424
  • 26.4 MPASM Assembler

    424
  • 26.5 MPLINK Object Linker/ MPLIB Object Librarian

    424
  • 26.6 MPLAB Assembler, Linker and Librarian for Various Device Families

    424
  • 26.7 MPLAB SIM Software Simulator

    425
  • 26.8 MPLAB REAL ICE In-Circuit Emulator System

    425
  • 26.9 MPLAB ICD 3 In-Circuit Debugger System

    425
  • 26.10 PICkit 3 In-Circuit Debugger/ Programmer and PICkit 3 Debug Express

    425
  • 26.11 PICkit 2 Development Programmer/Debugger and PICkit 2 Debug Express

    426
  • 26.12 MPLAB PM3 Device Programmer

    426
  • 26.13 Demonstration/Development Boards, Evaluation Kits, and Starter Kits

    426
• 27.0 Electrical Characteristics

  427
  • Absolute Maximum Ratings (†)

    427
    • FIGURE 27-1: PIC18LF2X/4XK22 Family Voltage-Frequency Graph (Industrial Temperature)

      428
    • FIGURE 27-2: PIC18LF2X/4XK22 Family Voltage-Frequency Graph (Extended Temperature)

      428
    • FIGURE 27-3: PIC18F2X/4XK22 Family Voltage-Frequency Graph (Industrial Temperature)

      429
    • FIGURE 27-4: PIC18F2X/4XK22 Family Voltage-Frequency Graph (Extended Temperature)

      429
  • 27.1 DC Characteristics: Supply Voltage, PIC18(L)F2X/4XK22

    430
  • 27.2 DC Characteristics: Power-Down Current, PIC18(L)F2X/4XK22

    431
  • 27.3 DC Characteristics: RC Run Supply Current, PIC18(L)F2X/4XK22

    433
  • 27.4 DC Characteristics: RC Idle Supply Current, PIC18(L)F2X/4XK22

    435
  • 27.5 DC Characteristics: Primary Run Supply Current, PIC18(L)F2X/4XK22

    437
  • 27.6 DC Characteristics: Primary Idle Supply Current, PIC18(L)F2X/4XK22

    438
  • 27.7 DC Characteristics: Secondary Oscillator Supply Current, PIC18(L)F2X/4XK22

    439
  • 27.8 DC Characteristics: Input/Output Characteristics, PIC18(L)F2X/4XK22

    441
  • 27.9 Memory Programming Requirements

    443
  • 27.10 Analog Characteristics

    444
    • TABLE 27-1: Comparator Specifications

      444
    • TABLE 27-2: DIGITAL-TO-ANALOG CONVERTER (DAC) Specifications

      444
    • TABLE 27-3: Fixed Voltage Reference (FVR) Specifications

      445
    • TABLE 27-4: CHARGE TIME MEASUREMENT UNIT (CTMU) Specifications

      445
    • FIGURE 27-5:

      446
    • TABLE 27-5: High/Low-Voltage Detect Characteristics

      446
  • 27.11 AC (Timing) Characteristics

    447
    • 27.11.1 Timing Parameter Symbology

      447
    • 27.11.2 Timing Conditions

      448
      • TABLE 27-6: Temperature and Voltage Specifications – AC

        448
      • FIGURE 27-6: Load Conditions for Device Timing Specifications

        448
    • 27.11.3 Timing Diagrams and Specifications

      449
      • FIGURE 27-7: External Clock Timing (All Modes Except PLL)

        449
      • TABLE 27-7: External Clock Timing Requirements

        449
      • TABLE 27-8: PLL Clock Timing Specifications

        450
      • TABLE 27-9: AC Characteristics: Internal Oscillators Accuracy PIC18(L)F46K22

        450
      • FIGURE 27-8: CLKOUT and I/O Timing

        451
      • TABLE 27-10: CLKOUT and I/O Timing Requirements

        451
      • FIGURE 27-9: Reset, Watchdog Timer, Oscillator Start-up Timer and Power-up Timer Timing

        452
      • FIGURE 27-10: Brown-out Reset Timing

        452
      • TABLE 27-11: Reset, Watchdog Timer, Oscillator Start-up Timer, Power-up Timer and Brown-out Reset Requirements

        453
      • FIGURE 27-11: Timer0 and Timer1 External Clock Timings

        453
      • TABLE 27-12: Timer0 and Timer1/3/5 External Clock Requirements

        454
      • FIGURE 27-12: Capture/Compare/PWM Timings (All CCP Modules)

        454
      • TABLE 27-13: Capture/Compare/PWM Requirements (All CCP Modules)

        455
      • FIGURE 27-13: Example SPI Master Mode Timing (CKE = 0)

        455
      • TABLE 27-14: Example SPI Mode Requirements (Master Mode, CKE = 0 or 1)

        456
      • FIGURE 27-14: Example SPI Master Mode Timing (CKE = 1)

        456
      • FIGURE 27-15: Example SPI Slave Mode Timing (CKE = 0)

        457
      • TABLE 27-15: Example SPI Mode Requirements (Slave Mode Timing, CKE = 0 or 1)

        457
      • FIGURE 27-16: Example SPI Slave Mode Timing (CKE = 1)

        458
      • FIGURE 27-17: I2C™ Bus Start/Stop Bits Timing

        458
      • TABLE 27-16: I2C™ Bus Start/Stop Bits Requirements (Slave Mode)

        459
      • FIGURE 27-18: I2C™ Bus Data Timing

        459
      • TABLE 27-17: I2C™ Bus Data Requirements (Slave Mode)

        460
      • FIGURE 27-19: Master SSP I2C™ Bus Start/Stop Bits Timing Waveforms

        461
      • TABLE 27-18: Master SSP I2C™ Bus Start/Stop Bits Requirements

        461
      • FIGURE 27-20: Master SSP I2C™ Bus Data Timing

        461
      • TABLE 27-19: Master SSP I2C™ Bus Data Requirements

        462
      • FIGURE 27-21: EUSART Synchronous Transmission (Master/Slave) Timing

        463
      • TABLE 27-20: EUSART Synchronous Transmission Requirements

        463
      • FIGURE 27-22: EUSART Synchronous Receive (Master/Slave) Timing

        463
      • TABLE 27-21: EUSART Synchronous Receive Requirements

        463
      • TABLE 27-22: A/D Converter Characteristics: PIC18(L)F2X/4XK22

        464
      • FIGURE 27-23: A/D Conversion Timing

        464
      • TABLE 27-23: A/D Conversion Requirements PIC18(L)F2X/4XK22

        465
• 28.0 DC and AC Characteristics Graphs and Charts

  467
• 29.0 Packaging Information

  523
  • 29.1 Package Marking Information

    523
  • 29.2 Package Details

    526
• Appendix A: Revision History

  545
  • Revision A (February 2010)

    545
  • Revision B (April 2010)

    545
  • Revision C (July 2010)

    545
  • Revision D (November 2010)

    545
  • Revision E (January 2012)

    545
  • Revision F (May 2012)

    545
• Appendix B: Device Differences

  546
  • TABLE B-1: Device Differences

    546
• INDEX

  547
  • A

    547
  • B

    547
  • C

    547
  • D

    549
  • E

    549
  • F

    550
  • G

    550
  • H

    550
  • I

    550
  • L

    551
  • M

    551
  • N

    551
  • O

    551
  • P

    551
  • R

    552
  • S

    553
  • T

    553
  • V

    555
  • W

    555
  • X

    555
• The Microchip Web Site

  557
• Customer Change Notification Service

  557
• Customer Support

  557
• Reader Response

  558
• Product Identification System

  559
• Worldwide Sales

  560