Freescale Semiconductor MPC830x PowerQUICC II Pro Processor Evaluation Kit MPC8309-KIT MPC8309-KIT Fiche De Données
Codes de produits
MPC8309-KIT
MPC8309 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 2
78
Freescale Semiconductor
Document revision history
27 Document revision history
The following table provides a revision history for this document.
Table 66. Document revision history
Rev.
No.
Date
Substantive Change(s)
2
09/2012
• In
, swapped CLK13 and CLK14.
• In
, removed the following test signals, as there are no corresponding use cases:
–
ECID_TMODE_IN
–
BOOT_ROM_ADDR[2] to BOOT_ROM_ADDR[12]
–
BOOT_ROM_RDATA[0] to BOOT_ROM_RDATA[31]
–
BOOT_ROM_MOD_EN, BOOT_ROM_RWB, BOOT_ROM_XFR_WAIT, BOOT_ROM_XFR_ERR
–
UC1_RM, UC2_RM, UC3_RM, UC5_RM, UC7_RM, AND URM_TRIG
–
TPR_SYS_AAD[0] to TPR_SYS_AAD[15]
–
TPR_SYS_SYNC, TPR_SYS_DACK
–
QE_TRB_0, QE_TRB_1
–
PLLCZ_CORE_CLKIN
–
JTAG_BISE, JTAG_PRPGPS, JTAG_BISR_TDO_EN
–
CLOCK_XLB_CLOCK_OUT
–
PD_XLB2MG_DDR_CLOCK
• In
, changed the following signal names as only QE-Based Fast Ethernet Controller is present
in this device:
–
–
TSEC_TMR_TRIG1 to FEC_TMR_TRIG1
–
TSEC_TMR_TRIG2 to FEC_TMR_TRIG2
–
TSEC_TMR_CLK to FEC_TMR_CLK
–
TSEC_TMR_GCLK to FEC_TMR_GCLK
–
TSEC_TMR_PP1 to FEC_TMR_PP1
–
TSEC_TMR_PP2 to FEC_TMR_PP2
–
TSEC_TMR_PP3 to FEC_TMR_PP3
–
TSEC_TMR_ALARM1 to FEC_TMR_ALARM1
–
TSEC_TMR_ALARM2 to FEC_TMR_ALARM2
–
FEC3_TMR_TX_ESFD to FEC2_TMR_TX_ESFD
FEC3_TMR_RX_ESFD to FEC2_TMR_RX_ESFD.
• In
, added parameteres t
LALEHOV
,, t
LALETOT
, and t
LBOTOT
and made the corresponding updates
• In
, replaced "32 X tSYS_CLK_IN" with "32 X tSYS_CLK_IN/PCI_SYNC_IN.
1
08/2011
• Updated QUICC Engine frequency in
.
• Updated QUICC Engine frequency from 200 MHz to 233 MHz in
.
.
• Updated QUICC Engine frequency to 233 MHz in
• Corrected LCCR to LCRR for all instances.
0
03/2011
Initial Release.