Analog Devices AD9253 Evaluation Board AD9253-125EBZ AD9253-125EBZ Fiche De Données

 

Rev. 0 | Page 37 of 40 

For additional information about functions controlled in 
Register 0x00 to Register 0xFF, see the 

Interfacing to High Speed ADCs via SPI.  

There are certain features in the map that can be set inde-
pendently for each channel, whereas other features apply 
globally to all channels (depending on context) regardless of 
which are selected. The first four bits in Register 0x05 can be 
used to select which individual data channels are affected. The 
output clock channels can be selected in Register 0x05 as well. A 
smaller subset of the independent feature list can be applied to 
those devices.  

All registers except Register 0x100 are updated the moment 
they are written. Setting Bit 0 of this transfer register high 
initializes the settings in the ADC sample rate override register 
(Address 0x100). 

If set, the external PDWN pin initiates power-down mode. If 
cleared, the external PDWN pin initiates standby mode. 

In normal operation (Bits[1:0] = 00), all ADC channels are 
active. 

In power-down mode (Bits[1:0] = 01), the digital datapath clocks 
are disabled while the digital datapath is reset. Outputs are 
disabled. 

In standby mode (Bits[1:0] = 10), the digital datapath clocks 
and the outputs are disabled. 

During a digital reset (Bits[1:0] = 11), all the digital datapath 
clocks and the outputs (where applicable) on the chip are reset, 
except the SPI port. Note that the SPI is always left under 
control of the user; that is, it is never automatically disabled or 
in reset (except by power-on reset). 

For applications that are sensitive to offset voltages and other 
low frequency noise, such as homodyne or direct conversion 
receivers, chopping in the first stage of the 

 is a feature 

that can be enabled by setting Bit 2. In the frequency domain, 
chopping translates offsets and other low frequency noise to 
f

CLK

/2 where it can be filtered. 

 

Setting this bit chooses LVDS-IEEE (reduced range) option. 
The default setting is LVDS-ANSI. As described in Table 18, 
when LVDS-ANSI or LVDS-IEEE reduced range link is selected, 
the user can select the driver termination. The driver current  
is automatically selected to give the proper output swing.  

0 LVDS-ANSI 

User 
selectable 

Automatically 
selected to give 
proper swing 

1 

LVDS-IEEE 
reduced 
range link 

User 
selectable 

Automatically 
selected to give 
proper swing 

Setting this bit inverts the output bit stream. 

By default, this bit is set to send the data output in twos 
complement format. Resetting this bit changes the output mode 
to offset binary. 

These bits allow the user to select the internal termination 
resistor.  

Bit 0 of the output adjust register controls the drive strength on 
the LVDS driver of the FCO and DCO outputs only. The default 
values set the drive to 1× while the drive can be increased to 2× 
by setting the appropriate channel bit in Register 0x05 and then 
setting Bit 0. These features cannot be used with the output 
driver termination select. The termination selection takes 
precedence over the 2× driver strength on FCO and DCO when 
both the output driver termination and output drive are selected.