Analog Devices AD9253 Evaluation Board AD9253-125EBZ AD9253-125EBZ Fiche De Données

 

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Before starting design and layout of the 

 as a system,  

it is recommended that the designer become familiar with these 
guidelines, which describes the special circuit connections and 
layout requirements that are needed for certain pins. 

When connecting power to the 

, it is recommended 

that two separate 1.8 V supplies be used. Use one supply for 
analog (AVDD); use a separate supply for the digital outputs 
(DRVDD). For both AVDD and DRVDD, several different 
decoupling capacitors should be used to cover both high and 
low frequencies. Place these capacitors close to the point of 
entry at the PCB level and close to the pins of the part, with 
minimal trace length. 

A single PCB ground plane should be sufficient when using the 

. With proper decoupling and smart partitioning of the 

PCB analog, digital, and clock sections, optimum performance 
is easily achieved. 

It is required that the exposed pad on the underside of the ADC 
be connected to analog ground (AGND) to achieve the best 
electrical and thermal performance of the 

. An exposed 

continuous copper plane on the PCB should mate to the 

 exposed pad, Pin 0. The copper plane should have 

several vias to achieve the lowest possible resistive thermal path 
for heat dissipation to flow through the bottom of the PCB. 
These vias should be solder-filled or plugged. 

To maximize the coverage and adhesion between the ADC and 
PCB, partition the continuous copper plane by overlaying a 
silkscreen on the PCB into several uniform sections. This provides 
several tie points between the ADC and PCB during the reflow 
process, whereas using one continuous plane with no partitions 
only guarantees one tie point. See Figure 75 for a PCB layout 
example. For detailed information on packaging and the PCB 
layout of chip scale packages, see the 

, 

A Design and Manufacturing Guide for the Lead Frame Chip 
Scale Package (LFCSP), at 

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The VCM pin should be decoupled to ground with a 0.1 μF 
capacitor. 

The VREF pin should be externally decoupled to ground with a 
low ESR, 1.0 μF capacitor in parallel with a low ESR, 0.1 μF 
ceramic capacitor.  

The SPI port should not be active during periods when the full 
dynamic performance of the converter is required. Because the 
SCLK, CSB, and SDIO signals are typically asynchronous to the 
ADC clock, noise from these signals can degrade converter 
performance. If the on-board SPI bus is used for other devices, 
it may be necessary to provide buffers between this bus and the 

 to keep these signals from transitioning at the con-

verter inputs during critical sampling periods. 

 is available in a 48-lead LFCSP package with the 

input pairs on either corner of the chip. See Figure 9 for the pin 
configuration. To maximize the crosstalk performance on the 
board, add grounded filled vias in between the adjacent 
channels as shown in Figure 76. 

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