Analog Devices AD9233 Evaluation Board AD9233-80EBZ AD9233-80EBZ Fiche De Données
Codes de produits
AD9233-80EBZ
AD9233
Rev. A | Page 22 of 44
TIMING
The lowest typical conversion rate of the AD9233 is 10 MSPS.
At clock rates below 10 MSPS, dynamic performance can
degrade.
At clock rates below 10 MSPS, dynamic performance can
degrade.
The AD9233 provides latched data outputs with a pipeline delay
of 12 clock cycles. Data outputs are available one propagation
delay (t
of 12 clock cycles. Data outputs are available one propagation
delay (t
PD
) after the rising edge of the clock signal.
The length of the output data lines and the loads placed on
them should be minimized to reduce transients within the
AD9233. These transients can degrade the dynamic performance
of the converter.
them should be minimized to reduce transients within the
AD9233. These transients can degrade the dynamic performance
of the converter.
Data Clock Output (DCO)
The AD9233 provides a data clock output (DCO) intended for
capturing the data in an external register. The data outputs are
valid on the rising edge of DCO, unless the DCO clock polarity
has been changed via the SPI. See Figure 2 for a graphical
timing description.
capturing the data in an external register. The data outputs are
valid on the rising edge of DCO, unless the DCO clock polarity
has been changed via the SPI. See Figure 2 for a graphical
timing description.