Atmel Xplained Pro Evaluation Kit ATSAM4E-XPRO ATSAM4E-XPRO Fiche De Données

1031

SAM4E [DATASHEET]

Atmel-11157D-ATARM-SAM4E16-SAM4E8-Datasheet_12-Jun-14

The polarity level of the fault inputs is configured by the FPOL field in the 

 (PWM_FMR).

For fault inputs coming from internal peripherals such as ADC, Timer Counter, to name but a few, the polarity level
must be FPOL = 1. For fault inputs coming from external GPIO pins the polarity level depends on the user's
implementation. 

The configuration of the Fault Activation Mode (FMOD field in PWMC_FMR) depends on the peripheral generating
the fault. If the corresponding peripheral does not have “Fault Clear” management, then the FMOD configuration to
use must be FMOD = 1, to avoid spurious fault detection. Check the corresponding peripheral documentation for
details on handling fault generation.

The fault inputs can be glitch filtered or not in function of the FFIL field in the PWM_FMR. When the filter is
activated, glitches on fault inputs with a width inferior to the PWM peripheral clock period are rejected.

A fault becomes active as soon as its corresponding fault input has a transition to the programmed polarity level. If
the corresponding bit FMOD is set to ‘0’ in the PWM_FMR, the fault remains active as long as the fault input is at
this polarity level. If the corresponding FMOD field is set to ‘1’, the fault remains active until the fault input is not at
this polarity level anymore and until it is cleared by writing the corresponding bit FCLR in the 

 (PWM_FCR). By reading the 

 (PWM_FSR), the user can read the current

level of the fault inputs by means of the field FIV, and can know which fault is currently active thanks to the FS field.

Each fault can be taken into account or not by the fault protection mechanism in each channel. To be taken into
account in the channel x, the fault y must be enabled by the bit FPEx[y] in the “PWM Fault Protection Enable
Registers” (PWM_FPE1). However the synchronous channels (see 

) do

not use their own fault enable bits, but those of the channel 0 (bits FPE0[y]).

The fault protection on a channel is triggered when this channel is enabled and when any one of the faults that are
enabled for this channel is active. It can be triggered even if the PWM peripheral clock is not running but only by a
fault input that is not glitch filtered.

When the fault protection is triggered on a channel, the fault protection mechanism resets the counter of this
channel and forces the channel outputs to the values defined by the fields FPVHx and FPVLx in the 

 (PWM_FPV) and fields FPZHx/FPZLx in the 

as shown in 

. The output forcing is made asynchronously to the channel counter. 

CAUTION:



To prevent an unexpected activation of the status flag FSy in the PWM_FSR, the FMODy bit can be set to ‘1’ 
only if the FPOLy bit has been previously configured to its final value.



To prevent an unexpected activation of the Fault Protection on the channel x, the bit FPEx[y] can be set to ‘1’ 
only if the FPOLy bit has been previously configured to its final value.

If a comparison unit is enabled (see 

) and if a fault is triggered in the

channel 0, then the comparison cannot match.

As soon as the fault protection is triggered on a channel, an interrupt (different from the interrupt generated at the
end of the PWM period) can be generated but only if it is enabled and not masked. The interrupt is reset by reading
the interrupt status register, even if the fault which has caused the trigger of the fault protection is kept active.

0

0

0

0

1

1

1

–

High impedance state (Hi-Z)