Atmel Xplained Pro Evaluation Kit ATSAM4E-XPRO ATSAM4E-XPRO Fiche De Données

1091

SAM4E [DATASHEET]

Atmel-11157D-ATARM-SAM4E16-SAM4E8-Datasheet_12-Jun-14

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The bit CES defines when the channel counter event occurs when the period is center-aligned (flag CHIDx in 

CALG = 0 (Left Alignment):

0/1: The channel counter event occurs at the end of the PWM period.

CALG = 1 (Center Alignment):

0: The channel counter event occurs at the end of the PWM period.

1: The channel counter event occurs at the end of the PWM period and at half the PWM period.

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When the period is center aligned, the bit UPDS defines when the update of the duty cycle, the polarity and the additional 
edge value/mode occurs after writing the corresponding update registers. 

CALG = 0 (Left Alignment):

0/1: The update always occurs at the end of the PWM period after writing the update register(s).

CALG = 1 (Center Alignment):

0: The update occurs at the next end of the PWM period after writing the update register(s).

1: The update occurs at the next end of the PWM half period after writing the update register(s).

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0: The dead-time generator is disabled.

1: The dead-time generator is enabled.

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0: The dead-time PWMHx output is not inverted.

1: The dead-time PWMHx output is inverted.

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0: The dead-time PWMLx output is not inverted.

1: The dead-time PWMLx output is inverted.