Atmel Xplained Pro Evaluation Kit ATSAM4E-XPRO ATSAM4E-XPRO Fiche De Données
Codes de produits
ATSAM4E-XPRO
SAM4E [DATASHEET]
Atmel-11157D-ATARM-SAM4E16-SAM4E8-Datasheet_12-Jun-14
1210
interrupt bit 12 of the Interrupt Status Register. Pause frames received with zero quantum are indicated on bit 13 of
the Interrupt Status Register.
the Interrupt Status Register.
Once the Pause Time Register is loaded and the frame currently being transmitted has been sent, no new frames
are transmitted until the pause time reaches zero. The loading of a new pause time, and hence the pausing of
transmission, only occurs when the GMAC is configured for full duplex operation. If the GMAC is configured for
half duplex there will be no transmission pause, but the pause frame received interrupt will still be triggered. A valid
pause frame is defined as having a destination address that matches either the address stored in Specific Address
Register 1 or if it matches the reserved address of 0x0180C2000001. It must also have the MAC control frame
type ID of 0x8808 and have the pause opcode of 0x0001.
are transmitted until the pause time reaches zero. The loading of a new pause time, and hence the pausing of
transmission, only occurs when the GMAC is configured for full duplex operation. If the GMAC is configured for
half duplex there will be no transmission pause, but the pause frame received interrupt will still be triggered. A valid
pause frame is defined as having a destination address that matches either the address stored in Specific Address
Register 1 or if it matches the reserved address of 0x0180C2000001. It must also have the MAC control frame
type ID of 0x8808 and have the pause opcode of 0x0001.
Pause frames that have frame check sequence (FCS) or other errors will be treated as invalid and will be
discarded. 802.3 Pause frames that are received after Priority-based Flow Control (PFC) has been negotiated will
also be discarded. Valid pause frames received will increment the pause frames received statistic register.
discarded. 802.3 Pause frames that are received after Priority-based Flow Control (PFC) has been negotiated will
also be discarded. Valid pause frames received will increment the pause frames received statistic register.
The pause time register decrements every 512 bit times once transmission has stopped. For test purposes, the
retry test bit can be set (bit 12 in the Network Configuration Register) which causes the Pause Time Register to
decrement every GTXCK cycle once transmission has stopped.
retry test bit can be set (bit 12 in the Network Configuration Register) which causes the Pause Time Register to
decrement every GTXCK cycle once transmission has stopped.
The interrupt (bit 13 in the Interrupt Status Register) is asserted whenever the Pause Time Register decrements to
zero (assuming it has been enabled by bit 13 in the Interrupt Mask Register). This interrupt is also set when a zero
quantum pause frame is received.
zero (assuming it has been enabled by bit 13 in the Interrupt Mask Register). This interrupt is also set when a zero
quantum pause frame is received.
43.5.15.2 802.3 Pause Frame Transmission
Automatic transmission of pause frames is supported through the transmit pause frame bits of the Network Control
Register. If either bit 11 or bit 12 of the Network Control Register is written with logic 1, an 802.3 pause frame will
be transmitted, providing full duplex is selected in the Network Configuration Register and the transmit block is
enabled in the Network Control Register.
Register. If either bit 11 or bit 12 of the Network Control Register is written with logic 1, an 802.3 pause frame will
be transmitted, providing full duplex is selected in the Network Configuration Register and the transmit block is
enabled in the Network Control Register.
Pause frame transmission will happen immediately if transmit is inactive or if transmit is active between the current
frame and the next frame due to be transmitted.
frame and the next frame due to be transmitted.
Transmitted pause frames comprise the following:
A destination address of 01-80-C2-00-00-01
A source address taken from Specific Address Register 1
A type ID of 88-08 (MAC control frame)
A pause opcode of 00-01
A pause quantum register
Fill of 00 to take the frame to minimum frame length
Valid FCS
The pause quantum used in the generated frame will depend on the trigger source for the frame as follows:
If bit 11 is written with a one, the pause quantum will be taken from the Transmit Pause Quantum Register.
The Transmit Pause Quantum Register resets to a value of 0xFFFF giving maximum pause quantum as
default.
The Transmit Pause Quantum Register resets to a value of 0xFFFF giving maximum pause quantum as
default.
If bit 12 is written with a one, the pause quantum will be zero.
After transmission, a pause frame transmitted interrupt will be generated (bit 14 of the Interrupt Status Register)
and the only statistics register that will be incremented will be the Pause Frames Transmitted Register.
and the only statistics register that will be incremented will be the Pause Frames Transmitted Register.
Pause frames can also be transmitted by the MAC using normal frame transmission methods.