Atmel Xplained Pro Evaluation Kit ATSAM4E-XPRO ATSAM4E-XPRO Fiche De Données

1229

SAM4E [DATASHEET]

Atmel-11157D-ATARM-SAM4E16-SAM4E8-Datasheet_12-Jun-14

GMAC_TSR

0x40034014

Access: Read/Write



Set when a transmit buffer descriptor is read with its used bit set. Writing a one clears this bit.



Set by the assertion of collision. Writing a one clears this bit. When operating in 10/100 mode, this status indicates either a 
collision or a late collision. 



Writing a one clears this bit.



Transmit go, if high transmit is active. When using FIFO, this bit represents bit 3 of the Network Control Register. When 
using the DMA interface this bit represents the TXGO variable as specified in the transmit buffer description.



Transmit frame corruption due to AHB error. Set if an error occurs while midway through reading transmit frame from the 
AHB, including HRESP errors and buffers exhausted mid frame (if the buffers run out during transmission of a frame then 
transmission stops, FCS shall be bad and GTXER asserted). 

Writing a one clears this bit.



Set when a frame has been transmitted. Writing a one clears this bit.



This bit is set if the transmitter was forced to terminate a frame that it had already began transmitting due to further data 
being unavailable.

This bit is set if a transmitter status write back has not completed when another status write back is attempted.

When using the DMA interface configured for internal FIFO mode, this bit is also set when the transmit DMA has written the 
SOP data into the FIFO and either the AHB bus was not granted in time for further data, or because an AHB not OK 
response was returned, or because a used bit was read.

31

30

29

28

27

26

25

24

–

–

–

–

–

–

–

–

23

22

21

20

19

18

17

16

–

–

–

–

–

–

–

–

15

14

13

12

11

10

9

8

–

–

–

–

–

–

–

HRESP

7

6

5

4

3

2

1

0

–

UND

TXCOMP

TFC

TXGO

RLE

COL

UBR